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getvictor edited this page Aug 17, 2013 · 33 revisions

Quick Start
FAQ

Features

EDA Playground gives engineers immediate hands-on exposure to simulating Verilog/SystemVerilog/VHDL. All you need is a web browser. The goal is to accelerate learning of design/testbench development with easier code sharing, and with simpler access to simulators and libraries.

  • With a simple click, run your code and see console output in real time. Pick another simulator version and run it again.
  • Save your code snippets. Share your code and simulation results with a web link. Perfect for web forum discussions or emails. Great for asking questions or sharing your knowledge.
  • Quickly try something out
    • Try out a SystemVerilog feature before using it on your project.
    • Try out a library that you're thinking of using.
    • Modify another engineer's shared code and re-run it.
  • Eliminate environment differences. Since the code always executes in the same environment, everyone will see the same result on a subsequent re-run.
  • Browse and use a large repository of working code examples and templates.

Playground

Usage Examples

  • Quick prototyping -- try out syntax or a library/language feature before using it in a large code base.
  • When asking questions on Stack Overflow or other online forums, attach a link to the code and simulation results. Results from a private EDA Playground deployment can also be posted on www.edaplayground.com
  • Use during technical interviews to test candidates' Verilog/SystemVerilog coding skills.
  • Run anywhere. When away from your work machine, you can still try a quick prototype on EDA Playground.
  • Create a Verilog lab for young engineers, with the Verilog code hosted on EDA Playground. Students can work from home at their own pace, and run the lab samples on EDA Playground.

What Users are Saying

EDA Playground is sooo useful for interviews. I got a lot more feedback from being able to watch someone compile and debug errors. I would highly recommend others to use it if they are asking SV related questions.

-Ricardo Goto, MTS at AMD (using private deployment)

I work in a large environment where compiles and sims take a considerable amount of time. When I'm developing/debugging, sometimes I want to use Verilog/SystemVerilog syntax that I have not used before. (Examples: wild equality, binding to the same port multiple times.) I don't want to stick my code into the environment and hope that the the feature works like I think it does. Instead, I first do a quick prototype on EDA Playground.

-Design Verification Engineer (using private deployment)

Simulators

The following simulators can be used.

On public EDA Playground -- The FREE Verilog IDE:

On private EDA Playground:

  • All simulators available on public version.
  • Any additional simulators that your company/university has licenses for or developed in-house.

Feature Requests and Bug Fixes

Request new features and bug fixes here: https://github.com/getvictor/eda-playground/issues
Or Tweet to @EDAPlayground

Credits

EDA Playground was created in May 2013 by Victor Lyuboslavsky.
EDA Playground on Twitter
Victor EDA on LinkedIn

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