The riscv spec clearly states that

"When multiple floating-point precisions are supported, then valid values of narrower n-bit types,
n<FLEN, are represented in the lower n bits of an FLEN-bit NaN value, in a process termed NaN-
boxing. The upper bits of a valid NaN-boxed value must be all 1s. Valid NaN-boxed n-bit values
therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value, n < m ≤
FLEN. Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost
FLEN-n bits to yield a legal NaN-boxedvalue"

[1]

It specifically states that

"Floating-point n-bit transfer operations move external values held in IEEE standard formats into and
out of the f registers, and comprise floating-point loads and stores (FLn/FSn) and floating-point move
instructions (FMV.n.X/FMV.X.n). A narrower n-bit transfer, n<FLEN, into the f registers will create a
valid NaN-boxed value. A narrower n-bit transfer out of the floating-point registers will transfer the
lower n bits of the register ignoring the upper FLEN-n bits"

[1]

, yet this project deals with narrower stores (fsw) by performing a double to single precision conversion,

The spec further states about other floating point operations that

"Apart from transfer operations described in the previous paragraph, all other floating-point operations
on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all
upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value,
otherwise the input value is treated as an n-bit canonical NaN."

[1]

however this project implements single precision floating point operations like fadd.s by performing double to single precision conversion.

If the non-standard behavior is intentional, at least the fmv.w.x instruction should be updated to perform a single to double precision conversion, as the current logic can and will have confusing results when moving floats that for example could be constructed in integer registers first.

[1] (https://github.com/riscv/riscv-isa-manual/releases/download/20240411/unpriv-isa-asciidoc.pdf, page 120, section 21.2. "NaN Boxing of Narrower Values")