CachePadded aligns aarch64 to 64 instead of 128

[xpepermint]

Ref: #1138

[taiki-e]

If we revert align of AArch64, we need to address the following comment explaining why we are currently using 128 in AArch64.

crossbeam/crossbeam-utils/src/cache_padded.rs

Lines 70 to 73 in abf24e1

	// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
	//
	// Sources:
	// - https://www.mono-project.com/news/2016/09/12/arm64-icache/

[taiki-e]

Considering that the cache line size of the Apple M1 actually seems to be 128 bytes, your guess at #1138 regarding the problem you encountered is probably wrong and doing this does not seem right.

$ sysctl machdep.cpu.brand_string
machdep.cpu.brand_string: Apple M1 (Virtual)

$ sysctl hw.cachelinesize
hw.cachelinesize: 128

$ sysctl machdep.cpu.brand_string
machdep.cpu.brand_string: Apple M1 Pro

$ sysctl hw.cachelinesize
hw.cachelinesize: 128