CachePadded: Use 128-byte alignment on arm64ec

Same as aarch64.
crossbeam-rs · Dec 8, 2024 · 0f81a69 · 0f81a69
1 parent 58bd8cf
commit 0f81a69
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/crossbeam-utils/src/cache_padded.rs b/crossbeam-utils/src/cache_padded.rs
@@ -67,7 +67,7 @@ use core::ops::{Deref, DerefMut};
 // - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
 // - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
 //
-// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
+// aarch64/arm64ec's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
 //
 // Sources:
 // - https://www.mono-project.com/news/2016/09/12/arm64-icache/
@@ -81,6 +81,7 @@ use core::ops::{Deref, DerefMut};
     any(
         target_arch = "x86_64",
         target_arch = "aarch64",
+        target_arch = "arm64ec",
         target_arch = "powerpc64",
     ),
     repr(align(128))
@@ -130,6 +131,7 @@ use core::ops::{Deref, DerefMut};
     not(any(
         target_arch = "x86_64",
         target_arch = "aarch64",
+        target_arch = "arm64ec",
         target_arch = "powerpc64",
         target_arch = "arm",
         target_arch = "mips",