Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

BX synchronization #64

Merged
merged 3 commits into from
Oct 28, 2024
Merged

BX synchronization #64

merged 3 commits into from
Oct 28, 2024

Conversation

mcoshiro
Copy link
Contributor

Small changes to VHDL top file generation to allow tf_merge_streamer modules to receive TP_bx_vld and pass the delayed TP_bx_vld to the top-level output.

Due to lack of familiarity with the VHDL generation scripts, the way the delayed TP_bx_vld (TP_bx_vld_merged) is passed from the first tf_merge_streamer module to the output is rather hacky. Any suggestions as to how to fix this are welcome.

WriteVHDLSyntax.py Outdated Show resolved Hide resolved
Copy link
Contributor

@aehart aehart left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This looks good to me. I'll hold off merging though until cms-L1TK/firmware-hls#349 is settled, in case any additional changes are needed here.

@jasonfan393 jasonfan393 merged commit 174c325 into master Oct 28, 2024
1 check passed
@jasonfan393
Copy link
Contributor

merging since firmware_hls #349 is settled, and just needs updated submodule.

@aehart aehart mentioned this pull request Oct 29, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants