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update for new binned memories and first split-fpga chain #57

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merged 19 commits into from
Feb 22, 2024

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jasonfan393
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PR (corresponding with firmware_hls 315 adds capability to handle new binned memory module. An additional flag is added to generator_hdl.py to enable the creation of a first half split-fpga chain. This chain is from IR to TP, and excludes the VMSME and TPROJ memories that will instead be calculated on the second device.

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Thanks, @jasonfan393. Looks good. Approved!

@aehart aehart merged commit 1b0164f into master Feb 22, 2024
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@aehart aehart deleted the New_Binned_Memory_Rebase branch February 22, 2024 10:21
@jasonfan393 jasonfan393 mentioned this pull request Mar 22, 2024
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2 participants