Updates to remove the generate statements used to instantiate memory …

…modules

bodge/TF_L1L2_tb_writer.vhd.bodge

@@ -2,14 +2,14 @@
   -- (Needed to compare with emData/).
   writeTF_L1L2_464 : entity work.FileWriterFIFO
   generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(L1L2)&outputFileNameEnding,
+    FILE_NAME  => FILE_OUT_TF&"L1L2"&outputFileNameEnding,
     FIFO_WIDTH  => 478
   )
   port map (
     CLK => CLK,
     DONE => FT_DONE,
-    WRITE_EN => TW_98_stream_A_write(L1L2),
-    FULL_NEG => TW_98_stream_A_full_neg(L1L2),
-    DATA => TW_98_stream_AV_din(L1L2)&BW_46_stream_AV_din(L1L2_L3)&BW_46_stream_AV_din(L1L2_L4)&BW_46_stream_AV_din(L1L2_L5)&BW_46_stream_AV_din(L1L2_L6)&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
+    WRITE_EN => TW_L1L2_stream_A_write,
+    FULL_NEG => TW_L1L2_stream_A_full_neg,
+    DATA => TW_L1L2_stream_AV_din&BW_L1L2_L3_stream_AV_din&BW_L1L2_L4_stream_AV_din&BW_L1L2_L5_stream_AV_din&BW_L1L2_L6_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
   );
 

bodge/TF_L2L3_tb_writer.vhd.bodge

@@ -2,14 +2,14 @@
   -- (Needed to compare with emData/).
   writeTF_L2L3_418 : entity work.FileWriterFIFO
   generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(L2L3)&outputFileNameEnding,
+    FILE_NAME  => FILE_OUT_TF&"L2L3"&outputFileNameEnding,
     FIFO_WIDTH  => 432
   )
   port map (
     CLK => CLK,
     DONE => FT_DONE,
-    WRITE_EN => TW_98_stream_A_write(L2L3),
-    FULL_NEG => TW_98_stream_A_full_neg(L2L3),
-    DATA => TW_98_stream_AV_din(L2L3)&BW_46_stream_AV_din(L2L3_L1)&BW_46_stream_AV_din(L2L3_L4)&BW_46_stream_AV_din(L2L3_L5)&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
+    WRITE_EN => TW_L2L3_stream_A_write,
+    FULL_NEG => TW_L2L3_stream_A_full_neg,
+    DATA => TW_L2L3_stream_AV_din&BW_L2L3_L1_stream_AV_din(&BW_L2L3_L4_stream_AV_din&BW_L2L3_L5_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
   );
 

bodge/TF_L3L4_tb_writer.vhd.bodge

@@ -2,14 +2,14 @@
   -- (Needed to compare with emData/).
   writeTF_L3L4_366 : entity work.FileWriterFIFO
   generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(L3L4)&outputFileNameEnding,
+    FILE_NAME  => FILE_OUT_TF&"L3L4"&outputFileNameEnding,
     FIFO_WIDTH  => 380
   )
   port map (
     CLK => CLK,
     DONE => FT_DONE,
-    WRITE_EN => TW_98_stream_A_write(L3L4),
-    FULL_NEG => TW_98_stream_A_full_neg(L3L4),
-    DATA => TW_98_stream_AV_din(L3L4)&BW_46_stream_AV_din(L3L4_L1)&BW_46_stream_AV_din(L3L4_L2)&BW_46_stream_AV_din(L3L4_L5)&BW_46_stream_AV_din(L3L4_L6)&emptyDiskStub&emptyDiskStub
+    WRITE_EN => TW_L3L4_stream_A_write,
+    FULL_NEG => TW_L3L4_stream_A_full_neg,
+    DATA => TW_L3L4_stream_AV_din&BW_L3L4_L1_stream_AV_din&BW_L3L4_L2_stream_AV_din&BW_L3L4_L5_stream_AV_din&BW_L3L4_L6_stream_AV_din&emptyDiskStub&emptyDiskStub
   );
 

bodge/TF_L5L6_tb_writer.vhd.bodge

@@ -2,14 +2,14 @@
   -- (Needed to compare with emData/).
   writeTF_L5L6_268 : entity work.FileWriterFIFO
   generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(L5L6)&outputFileNameEnding,
+    FILE_NAME  => FILE_OUT_TF&"L5L6"&outputFileNameEnding,
     FIFO_WIDTH  => 282
   )
   port map (
     CLK => CLK,
     DONE => FT_DONE,
-    WRITE_EN => TW_98_stream_A_write(L5L6),
-    FULL_NEG => TW_98_stream_A_full_neg(L5L6),
-    DATA => TW_98_stream_AV_din(L5L6)&BW_46_stream_AV_din(L5L6_L1)&BW_46_stream_AV_din(L5L6_L2)&BW_46_stream_AV_din(L5L6_L3)&BW_46_stream_AV_din(L5L6_L4)
+    WRITE_EN => TW_L5L6_stream_A_write,
+    FULL_NEG => TW_L5L6_stream_A_full_neg,
+    DATA => TW_L5L6_stream_AV_din&BW_L5L6_L1_stream_AV_din&BW_L5L6_L2_stream_AV_din&BW_L5L6_L3_stream_AV_din&BW_L5L6_L4_stream_AV_din
   );
 

generator_hdl.py

@@ -127,18 +127,18 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict,
         if memInfo.is_initial:
             # Input arguments
             if "DL" in mtypeB: # DTCLink
-                string_input_mems += writeDTCLinkLHSPorts_interface(mtypeB)
+                string_input_mems += writeDTCLinkLHSPorts_interface(mtypeB, memDict)
             else:
-                string_input_mems += writeMemoryLHSPorts_interface(mtypeB)
+                string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB)
         elif memInfo.is_final:
             # Output arguments
             if memInfo.isFIFO:
-                string_output_mems += writeTrackStreamRHSPorts_interface(mtypeB)
+                string_output_mems += writeTrackStreamRHSPorts_interface(mtypeB, memDict)
             else:
                 string_output_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo)
         elif extraports:
             # Debug ports corresponding to BRAM inputs.
-            string_input_mems += writeMemoryLHSPorts_interface(mtypeB, extraports)            
+            string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB, extraports)            
 
     string_topmod_interface += string_ctrl_signals
     string_topmod_interface += string_input_mems
@@ -208,19 +208,20 @@ def writeTBMemoryReads(memDict, memInfoDict, initial_proc):
 
     for mtypeB in memDict:
         memInfo = memInfoDict[mtypeB]
+        memList = memDict[mtypeB]
 
         if memInfo.is_initial:
             first_mem = True if initial_proc in memInfo.downstream_mtype_short and not found_first_mem else False # first memory of the chain
-            string_read += writeTBMemoryReadInstance(mtypeB, memInfo.bxbitwidth, first_mem, memInfo.is_binned)
+            string_read += writeTBMemoryReadInstance(mtypeB, memDict, memInfo.bxbitwidth, first_mem, memInfo.is_binned)
 
             if first_mem: # Write start signal for the first memory in the chain
                 string_read += "  -- As all " + memInfo.mtype_short + " signals start together, take first one, to determine when\n"
                 if "DL" in memInfo.mtype_short: 
                     string_read += "  -- first event starts being read from the first link in the chain.\n"
-                    string_read += "  START_FIRST_LINK <= START_" + memInfo.mtype_short + "(enum_" + mtypeB + "'val(0));\n\n"
+                    string_read += "  START_FIRST_LINK <= START_" + memList[0].inst+";\n\n"
                 else:
                     string_read += "  -- first event starts being written to first memory in chain.\n"
-                    string_read += "  START_FIRST_WRITE <= START_" + memInfo.mtype_short + "(enum_" + mtypeB + "'val(0));\n\n" 
+                    string_read += "  START_FIRST_WRITE <= START_" + memList[0].inst+";\n\n" 
                 found_first_mem = True
 
     # string_read += "\n"
@@ -259,12 +260,13 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs):
     string_final = ""
 
     for mtypeB in memDict:
+        memList = memDict[mtypeB]
         memInfo = memInfoDict[mtypeB]
         proc = memInfo.upstream_mtype_short # Processing module that writes to mtypeB
         up_proc = notfinal_procs[notfinal_procs.index(proc)-1] if notfinal_procs and proc != notfinal_procs[0] and proc in notfinal_procs else "" # The previous processing module
 
         if memInfo.isFIFO:
-            string_tmp = writeTBMemoryWriteFIFOInstance(mtypeB, proc, memInfo.bxbitwidth)
+            string_tmp = writeTBMemoryWriteFIFOInstance(mtypeB, memDict, proc, memInfo.bxbitwidth)
             # A bodge for TrackBuilder to write TF concatenated track+stub data.
             # (Needed to compare with emData/).
             if mtypeB == 'TW_98':
@@ -285,7 +287,7 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs):
               string_intermediate += string_tmp
             else:
               is_cm = memInfo.downstream_mtype_short in ("TP", "MP")
-              string_intermediate += writeTBMemoryWriteInstance(mtypeB, proc, up_proc, memInfo.bxbitwidth, memInfo.is_binned, is_cm)
+              string_intermediate += writeTBMemoryWriteInstance(mtypeB, memList, proc, up_proc, memInfo.bxbitwidth, memInfo.is_binned, is_cm)
 
     string_write = "  -- Write signals to output .txt files\n\n"
     string_write += "  writeIntermediateRAMs : if INST_TOP_TF = 1 generate\n"