fix bugs with order of some signals

cms-L1TK · Feb 2, 2024 · 73ab85f · 73ab85f
1 parent 455aa11
commit 73ab85f
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Showing 2 changed files with 15 additions and 8 deletions.
diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py
@@ -858,6 +858,8 @@ def writeTBConstants(memDict, memInfoDict, procs, emData_dir, sector):
     string_constants += "  constant inputFileNameEnding".ljust(str_len) + ": string := \"_" + sector + ".dat\"; -- " + sector + " specifies the nonant/sector the testvectors represent\n"
     string_constants += "  constant outputFileNameEnding".ljust(str_len) + ": string := \".txt\";\n"
     string_constants += "  constant debugFileNameEnding".ljust(str_len) + ": string := \".debug.txt\";\n\n"
+    string_constants += "  signal dummy : STD_LOGIC := '0';\n\n -- dummy tb signal for inputs into sectorproc"
+    string_constants += "  signal dummyaddr : t_as_36_addr := (others => '0');\n\n -- dummy tb signal for inputs into sectorproc"
 
     return string_constants
 
@@ -1054,8 +1056,8 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc
         for memMod in memList:
             mem = memMod.inst
             if split and ("AS" in mtypeB and "n1" in mem):
-                    string_output += ("        "+mem+"_enb").ljust(str_len) + "=> open,\n"
-                    string_output += ("        "+mem+"_V_readaddr").ljust(str_len) + "=> open,\n"
+                    string_output += ("        "+mem+"_enb").ljust(str_len) + "=> dummy,\n"
+                    string_output += ("        "+mem+"_V_readaddr").ljust(str_len) + "=> dummyaddr,\n"
                     string_output += ("        "+mem+"_V_dout").ljust(str_len) + "=> open,\n"
                     string_output += ("        "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n"
             if memInfo.is_initial:
@@ -1320,11 +1322,16 @@ def writeProcMemoryLHSPorts(argname,mem,split = False):
     """
 
     string_mem_ports = ""
-    if ("TPROJ" in mem.inst or "VMSME" in mem.inst) and split: #set TPROJ and VMSME to open for a split-FPGA project
+    if ("TPROJ" in mem.inst) and split: #set TPROJ and VMSME to open for a split-FPGA project
           string_mem_ports += "      "+argname+"_dataarray_data_V_ce0       => open,\n"
           string_mem_ports += "      "+argname+"_dataarray_data_V_we0       => open,\n"
           string_mem_ports += "      "+argname+"_dataarray_data_V_address0  => open,\n"
           string_mem_ports += "      "+argname+"_dataarray_data_V_d0        => open,\n"
+    elif ("VMSME" in mem.inst and split):
+        string_mem_ports += "      "+argname+"_dataarray_0_data_V_ce0       => open,\n"
+        string_mem_ports += "      "+argname+"_dataarray_0_data_V_we0       => open,\n"
+        string_mem_ports += "      "+argname+"_dataarray_0_data_V_address0  => open,\n"
+        string_mem_ports += "      "+argname+"_dataarray_0_data_V_d0        => open,\n"
     elif "memoriesTEO" in argname or "memoryME" in argname :
         string_mem_ports += "      "+argname+"_dataarray_0_data_V_ce0       => open,\n"
         string_mem_ports += "      "+argname+"_dataarray_0_data_V_we0       => "

diff --git a/generator_hdl.py b/generator_hdl.py
@@ -133,11 +133,6 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict,
                 string_input_mems += writeDTCLinkLHSPorts_interface(mtypeB, memDict)
             else:
                 string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB)
-        if ("AS_36" in mtypeB and args.split): #for split fpga we want AS sent to second device
-          ASmemDict = {mtypeB : []}
-          for mem in memList: 
-            if "n1" in mem.inst: ASmemDict[mtypeB].append(mem)
-          string_input_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,  ASmemDict)
         elif memInfo.is_final:
             # Output arguments
             if memInfo.isFIFO:
@@ -149,6 +144,11 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict,
         elif extraports:
             # Debug ports corresponding to BRAM inputs.
             string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB, extraports)            
+        if ("AS_36" in mtypeB and args.split): #for split fpga we want AS sent to second device
+          ASmemDict = {mtypeB : []}
+          for mem in memList: 
+            if "n1" in mem.inst: ASmemDict[mtypeB].append(mem)
+          string_input_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,  ASmemDict)
 
     string_topmod_interface += string_ctrl_signals
     string_topmod_interface += string_input_mems