EMP FPGA2

IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile

@@ -4,7 +4,7 @@ input_file = mem/in.txt
 proj_path = ../../../../proj
 hls_script_path = ../../script
 
-all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion
+all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input
 
 $(core_dir):
 	@mkdir cgn mem
@@ -32,9 +32,6 @@ add_common_files:
 hdl_add_files: $(core_file)
 	cd hdl; ln -s ../../../hdl/*.vhd .
 
-lut_inclusion:
-	@python3 scripts/lut_copy.py
-
 $(input_file): $(core_dir)
 	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsCMBarrel/InputStubs -o $(input_file)
 
@@ -53,4 +50,4 @@ sim: $(input_file) $(core_file) $(core_dir)
 	@cd $(hls_script_path); vivado -mode batch -source runSim.tcl
 	@python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt
 
-.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input lut_inclusion core_patch
+.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch

IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl

@@ -1,16 +1,11 @@
 set_property SOURCE_SET sources_1 [get_filesets sim_1]
 add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/mem/in.txt
-set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl ]]
-append lut_script "/pre_msim.tcl"
-add_files -fileset utils_1 -norecurse $lut_script
-#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1]
-#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt
-set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]"
-eval ${pre_path}
 
 # Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
 set_property source_mgmt_mode None [current_project]
 set_property top top [get_filesets sim_1]
 set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
 # Re-enabling previously disabled source management mode.
 set_property source_mgmt_mode All [current_project]

IntegrationTests/DualFPGA/firmware/Makefile

@@ -0,0 +1,65 @@
+core_file_fpga1 = scripts/xciMaker_fpga1
+core_file_fpga2 = scripts/xciMaker_fpga2
+core_dir = cgn
+input_file_fpga1 = mem/in_fpga1.txt
+input_file_fpga2 = mem/in_fpga2.txt
+fpga1_hls_script_path = ../../CombinedConfig_FPGA1/script 
+fpga2_hls_script_path = ../../CombinedConfig_FPGA2/script
+
+all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2 
+
+fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1
+
+fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2 
+
+$(core_dir):
+	@mkdir cgn mem
+	@mkdir cgn/f1
+	@mkdir cgn/f2
+	@cd mem; ln -s ../../../../emData/LUTsSplit LUTs
+	@cd mem; ln -s ../../../../emData/MemPrintsSplit MemPrintsSplit
+	@cd hdl; ln -s ../../../common common
+
+$(core_file_fpga1): $(core_dir)
+	make -C $(fpga1_hls_script_path) -j 24 Work
+	@python3 scripts/include_cores.py -s $(fpga1_hls_script_path) -o $(core_file_fpga1) -f f1
+
+$(core_file_fpga2): $(core_dir)
+	make -C $(fpga2_hls_script_path) -j 24 Work
+	@python3 scripts/include_cores.py -s $(fpga2_hls_script_path) -o $(core_file_fpga2) -f f2
+
+kfin_adj:
+	@python3 scripts/kf_link_mod.py
+
+xciCreation_fpga1: $(core_file_fpga1)
+	make -f $(core_file_fpga1) -j 8 all
+
+xciCreation_fpga2: $(core_file_fpga2)
+	make -f $(core_file_fpga2) -j 8 all
+
+add_common_files:
+	@if [ ! -d ucf ]; then mkdir ucf; fi
+	@cd ucf; ln -s ../../../common/ucf/*.tcl .
+	@cd scripts; ln -s ../../../common/script/emp/* .
+
+hdl_add_files_fpga1: $(core_file)
+	cd hdl; ln -s ../../../CombinedConfig_FPGA1/hdl/SectorProcessor.vhd SectorProcessor_f1.vhd
+	cd hdl; ln -s ../../../CombinedConfig_FPGA1/hdl/memUtil_pkg.vhd memUtil_pkg_f1.vhd
+
+hdl_add_files_fpga2: $(core_file)
+	cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/SectorProcessor.vhd SectorProcessor_f2.vhd
+	cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/memUtil_pkg.vhd memUtil_pkg_f2.vhd
+
+$(input_file_fpga1): $(core_dir)
+	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsSplit/InputStubs -o $(input_file_fpga1)
+
+$(input_file_fpga2): $(core_dir)
+	@python3 scripts/convert_emData2EMP_Link_FPGA2.py -d mem/MemPrintsSplit/ -o $(input_file_fpga2)
+
+apollo_input_fpga1: $(input_file_fpga1)
+	@python3 scripts/split_emp_input.py -i $(input_file_fpga1) -o mem/in_fpga1_
+
+apollo_input_fpga2: $(input_file_fpga2)
+	@python3 scripts/split_emp_input.py -i $(input_file_fpga2) -o mem/in_fpga2_
+
+.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2 

IntegrationTests/DualFPGA/firmware/cfg/apollo.dep

@@ -0,0 +1,15 @@
+# common for both FPGAs
+
+
+src -c emp-fwk:components/datapath emp_data_types.vhd
+src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
+
+include -c ipbus-firmware:components/ipbus_slaves ipbus_syncreg_v.dep ipbus_ctrlreg_v.dep ipbus_reg_v.dep ipbus_freq_ctr.dep
+
+#src ../constrs/floorplan_emp
+
+include -c emp-fwk:components/links/slink slink.dep
+
+addrtab -c emp-fwk:components/payload emp_payload.xml
+
+

IntegrationTests/DualFPGA/firmware/cfg/apollo_f1.dep

@@ -0,0 +1,8 @@
+
+include payload_f1.dep
+src emp_project_decl_f1.vhd
+setup ../ucf/ip.tcl
+
+include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep
+
+include apollo.dep

IntegrationTests/DualFPGA/firmware/cfg/apollo_f2.dep

@@ -0,0 +1,8 @@
+
+include payload_f2.dep
+src emp_project_decl_f2.vhd
+setup ../ucf/ip.tcl
+
+include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p2_2.dep
+
+include apollo.dep

IntegrationTests/DualFPGA/firmware/cfg/payload_f1.dep

@@ -0,0 +1,29 @@
+#Payload and top level
+src payload_f1.vhd
+src tf1_wrapper.vhd
+src linktosecproc.vhd
+src secproc1tolink.vhd
+src --vhdl2008 SectorProcessor_f1.vhd
+#src common/hdl/emp/pkgs/tf_interface_pkg.vhd
+src memUtil_pkg_f1.vhd
+src memUtil_aux_pkg_f1.vhd
+src common/hdl/emp/pkgs/GCU_utils.vhd
+src conv_pkg_f1.vhd
+include -c firmware-hls:KalmanFilter/common components.dep 
+
+#Track Builder dependencies
+src common/hdl/CreateStartSignal.vhd
+#src --vhdl2008 common/hdl/tf_lut.vhd
+src --vhdl2008 common/hdl/tf_mem_bin.vhd
+src --vhdl2008 common/hdl/tf_mem_format.vhd
+src --vhdl2008 common/hdl/tf_mem.vhd
+src --vhdl2008 common/hdl/tf_merge_streamer.vhd
+src common/hdl/tf_pkg.vhd
+src --vhdl2008 common/hdl/tf_pipe_delay.vhd
+
+################
+# Include Cores
+################
+iprepo *
+src ../cgn/f1/*/*/*.xci
+

IntegrationTests/DualFPGA/firmware/cfg/payload_f2.dep

@@ -0,0 +1,40 @@
+src memUtil_pkg_f2.vhd
+src memUtil_aux_pkg_f2.vhd
+src payload_f2.vhd
+src linktosecproc2.vhd
+src sp2_mem_writer.vhd
+src tf2_wrapper.vhd
+src --vhdl2008 SectorProcessor_f2.vhd
+src tf_to_kf.vhd
+src kf_wrapper.vhd
+src common/hdl/emp/pkgs/tf_interface_pkg.vhd
+src kf_input_merger.vhd
+
+# KF
+include -c firmware-hls:KalmanFilter/kfin components.dep 
+include -c firmware-hls:KalmanFilter/kf components.dep 
+include -c firmware-hls:KalmanFilter/kfout components.dep 
+include -c firmware-hls:KalmanFilter/tq components.dep 
+include -c firmware-hls:KalmanFilter/common components.dep 
+
+#Tracklet dependencies
+src common/hdl/CreateStartSignal.vhd
+#src --vhdl2008 common/hdl/tf_lut.vhd
+src --vhdl2008 common/hdl/tf_mem_bin.vhd
+src --vhdl2008 common/hdl/tf_mem_format.vhd
+src --vhdl2008 common/hdl/tf_mem.vhd
+src --vhdl2008 common/hdl/tf_mem_tproj.vhd
+src --vhdl2008 common/hdl/tf_mem_tpar.vhd
+src --vhdl2008 common/hdl/mem_reader.vhd
+src common/hdl/tf_pkg.vhd
+src --vhdl2008 common/hdl/tf_pipe_delay.vhd
+
+#Floorplan
+src ../ucf/floorplan_f2.tcl
+
+################
+# Include Cores
+################
+iprepo *
+src ../cgn/f2/*/*/*.xci
+

IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep

@@ -0,0 +1,14 @@
+#don't include cm_v2_p1_2 since without decoder, it will have unresolved tcds2 dependencies
+@fpga_position = "1"
+@fpga_speed_grade = "-2-e"
+
+include payload_f1.dep
+setup ../ucf/vsim_f1.tcl
+
+include -c emp-fwk:boards/testbench top.dep
+
+src tb_decl_f1.vhd
+src emp_project_decl_f1.vhd 
+src -c emp-fwk:components/links/slink emp_slink_types.vhd
+
+include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p1.dep

IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep

@@ -0,0 +1,14 @@
+#don't include cm_v2_p1_2 since without decoder, it will have unresolved tcds2 dependencies
+@fpga_position = "2"
+@fpga_speed_grade = "-2-e"
+
+include payload_f2.dep
+setup ../ucf/vsim_f2.tcl
+
+include -c emp-fwk:boards/testbench top.dep
+
+src tb_decl_f2.vhd
+src emp_project_decl_f2.vhd 
+src -c emp-fwk:components/links/slink emp_slink_types.vhd
+
+include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p2.dep

IntegrationTests/DualFPGA/firmware/hdl/conv_pkg_f1.vhd

@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.emp_data_types.all;
+use work.hybrid_data_types.all;
+
+package conv_pkg_f1 is
+
+  function conv_single (l : ldata)
+    return t_packet;
+
+end package conv_pkg_f1;
+
+package body conv_pkg_f1 is
+
+  function conv_single(l : ldata) return t_packet is
+    variable s : t_packet;
+  begin
+    s.valid          := l(68).valid;
+    s.start_of_orbit := l(68).start_of_orbit;
+    s.start          := l(68).start;
+    s.last           := l(68).last;
+    return s;
+  end;
+
+end package body conv_pkg_f1;
+
+
+
+

IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f1.vhd

@@ -0,0 +1,71 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+use work.emp_framework_decl.all;
+use work.emp_device_types.all;
+use work.emp_slink_types.all;
+
+package emp_project_decl is
+
+  constant PAYLOAD_REV : std_logic_vector(31 downto 0) := X"12345678";
+
+  -- Latency buffer size
+  constant LB_ADDR_WIDTH : integer := 10;
+
+  -- Clock setup
+  constant CLOCK_COMMON_RATIO : integer               := 36;
+  constant CLOCK_RATIO        : integer               := 6;
+  constant CLOCK_AUX_DIV      : clock_divisor_array_t := (18, 9, 4);  -- Dividers of CLOCK_COMMON_RATIO * 40 MHz
+
+  -- Readdjust if latency changes for FPGA1 algorithm
+  constant PAYLOAD_LATENCY : integer := 140;
+
+  -- F1 transmits to F2 on inter-fpga links
+  constant REGION_CONF : region_conf_array_t := (
+     0   => kDummyRegion,                     -- service c2c
+     1   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+     2   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+     3   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+     4   => kDummyRegion,                     -- not routed
+     5   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+     6   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+     7   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+     8   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+     9   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+    10   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+    11   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+    12   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+    13   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+    14   => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
+    15   => kDummyRegion,                     -- not routed
+------cross
+----- all MGTs instantiated bidirectionally for now
+    16  => kDummyRegion,                      -- not routed
+    17  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    18  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    19  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    20  => kDummyRegion,                      -- not routed                  
+    21  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    22  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    23  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    24  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    25  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    26  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    27  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    28  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    29  => (gty25, buf, no_fmt, buf, gty25),  -- firefly
+    30  => (gty25, buf, no_fmt, buf, gty25),  -- firefly     
+    31  => kDummyRegion,                      -- service tcds
+
+    others => kDummyRegion
+    );
+
+  -- Specify the slink quad using the corresponding region conf ID
+  -- Specify slink channels to enable using the channel mask
+  constant SLINK_CONF : slink_conf_array_t := (
+    others => kNoSlink
+    );
+
+
+end emp_project_decl;