Timing improvements #329
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Timing improvements #329
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aryd
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| port ( | ||
| clk: in std_logic; | ||
| --memory_din: in t_write; | ||
| rstb: in std_logic; | ||
| wea: in std_logic; | ||
| bxa: in std_logic_vector( 2 downto 0 ); -- set to bx_o | ||
| addra: in std_logic_vector( clogb2(RAM_DEPTH) - 1 downto 0 ); | ||
| dina: in std_logic_vector( RAM_WIDTH - 1 downto 0 ); | ||
| --memory_read: in t_read; | ||
| addrb: in std_logic_vector( clogb2(RAM_DEPTH) - 1 downto 0 ); | ||
| --memory_dout: out t_data | ||
| nent_o: out t_arr_7b(0 to NUM_PAGES-1); | ||
| doutb: out std_logic_vector( RAM_WIDTH - 1 downto 0 ) |
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This interface is changed to remove the sync_nent port. In the branch for the FPGA2 project I have changed the code such that it is not passing the address, rather the memory module now counts the number of entries and keep tracks of which BX to write the data to. This version would not be "mergable" with the FPGA2 project. We should discuss how to proceed. My motivation was to minimize the amount of data we need to route to the memories.
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This PR corresponds to cms-L1TK/project_generation_scripts#59 and makes the unbinned memory adapted from Thomas's work the default.
N.B.: To be merged after cms-L1TK/project_generation_scripts#59 and #315 are merged.
ETA: The updates to the unbinned memory module have been reverted for now. To be revisited once the outstanding dual-FPGA work is merged.