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Manually copied FPGA2-targeted changes from dual_fpga2_4_ryd_validupd…
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@mcoshiro
mcoshiro committed Oct 10, 2024
1 parent da5e96b commit ffde743
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6 changes: 5 additions & 1 deletion IntegrationTests/DualFPGA/firmware/cfg/payload_f2.dep
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Original file line number Diff line number Diff line change
Expand Up @@ -17,17 +17,21 @@ include -c firmware-hls:KalmanFilter/kfout components.dep
include -c firmware-hls:KalmanFilter/tq components.dep
include -c firmware-hls:KalmanFilter/common components.dep

#Track Builder dependencies
#Tracklet dependencies
src common/hdl/CreateStartSignal.vhd
#src --vhdl2008 common/hdl/tf_lut.vhd
src --vhdl2008 common/hdl/tf_mem_bin.vhd
src --vhdl2008 common/hdl/tf_mem_format.vhd
src --vhdl2008 common/hdl/tf_mem.vhd
src --vhdl2008 common/hdl/tf_mem_tproj.vhd
src --vhdl2008 common/hdl/tf_mem_tpar.vhd
src --vhdl2008 common/hdl/mem_reader.vhd
src common/hdl/tf_pkg.vhd
src --vhdl2008 common/hdl/tf_pipe_delay.vhd

#Floorplan
src ../ucf/floorplan_f2.tcl

################
# Include Cores
################
Expand Down
26 changes: 13 additions & 13 deletions IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f2.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -42,20 +42,20 @@ package emp_project_decl is
------cross
----- all MGTs instantiated bidirectionally for now
16 => kDummyRegion, -- not routed
17 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
18 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
19 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
17 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
18 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
19 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
20 => kDummyRegion, -- not routed
21 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
22 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
23 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
24 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
25 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
26 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
27 => (gty25, no_buf, no_fmt, buf, gty25), -- firefly
28 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
29 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
30 => (gty25, no_buf, no_fmt, no_buf, gty25), -- firefly
21 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
22 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
23 => (no_mgt, no_buf, no_fmt, buf, gty25), -- firefly
24 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
25 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
26 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
27 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
28 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
29 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
30 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
31 => kDummyRegion, -- service tcds

others => kDummyRegion
Expand Down
93 changes: 80 additions & 13 deletions IntegrationTests/DualFPGA/firmware/hdl/linktosecproc2.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,15 @@ use work.memUtil_aux_pkg_f2.all;

entity linktosecproc2 is
port(
clk : in std_logic;
rst : in std_logic;
d : in ldata(4 * N_REGION - 1 downto 0);
AS_36_link_data : out t_arr_AS_36_37b;
MPAR_73_link_data : out t_arr_MTPAR_73_76b;
bx_link_data : out std_logic_vector(2 downto 0);
valid : out std_logic
clk : in std_logic;
rst : in std_logic;
d : in ldata(4 * N_REGION - 1 downto 0);
AS_36_link_data : out t_arr_AS_36_37b;
MPAR_73_link_data : out t_arr_MTPAR_73_76b;
bx_link_data : out std_logic_vector(2 downto 0);
AS_36_link_valid : out t_arr_AS_36_1b;
MPAR_73_link_valid : out t_arr_MTPAR_73_1b;
bx_link_valid : out std_logic
);

end linktosecproc2;
Expand Down Expand Up @@ -95,10 +97,6 @@ begin
MTPAR_signals(63 + 15*64 downto 0 + 15*64) <= d(12).data(63 downto 0);
MTPAR_signals(63 + 16*64 downto 0 + 16*64) <= d(11).data(63 downto 0);
MTPAR_signals(63 + 17*64 - 12 downto 0 + 17*64) <= d(10).data(63 - 12 downto 0);

--latch bx_link_data when not valid
bx_link_data_int <= d(9).data(2 downto 0) when (d(9).valid='1') else bx_link_data_int;
bx_link_data <= bx_link_data_int;

AS_36_link_data(L1PHIAn1) <= AS_signals(36 downto 0);
AS_36_link_data(L1PHIBn1) <= AS_signals(73 downto 37);
Expand Down Expand Up @@ -149,6 +147,57 @@ begin
AS_36_link_data(D5PHICn1) <= AS_signals(1738 downto 1702);
AS_36_link_data(D5PHIDn1) <= AS_signals(1775 downto 1739);

--Note that since some AS words are built from data on multiple input links,
--only the valid from the first input is used
AS_36_link_valid(L1PHIAn1) <= d(59).valid;
AS_36_link_valid(L1PHIBn1) <= d(59).valid;
AS_36_link_valid(L1PHICn1) <= d(58).valid;
AS_36_link_valid(L1PHIDn1) <= d(58).valid;
AS_36_link_valid(L1PHIEn1) <= d(57).valid;
AS_36_link_valid(L1PHIFn1) <= d(57).valid;
AS_36_link_valid(L1PHIGn1) <= d(56).valid;
AS_36_link_valid(L1PHIHn1) <= d(55).valid;
AS_36_link_valid(L2PHIAn1) <= d(55).valid;
AS_36_link_valid(L2PHIBn1) <= d(54).valid;
AS_36_link_valid(L2PHICn1) <= d(54).valid;
AS_36_link_valid(L2PHIDn1) <= d(53).valid;
AS_36_link_valid(L3PHIAn1) <= d(53).valid;
AS_36_link_valid(L3PHIBn1) <= d(52).valid;
AS_36_link_valid(L3PHICn1) <= d(51).valid;
AS_36_link_valid(L3PHIDn1) <= d(51).valid;
AS_36_link_valid(L4PHIAn1) <= d(50).valid;
AS_36_link_valid(L4PHIBn1) <= d(50).valid;
AS_36_link_valid(L4PHICn1) <= d(49).valid;
AS_36_link_valid(L4PHIDn1) <= d(49).valid;
AS_36_link_valid(L5PHIAn1) <= d(48).valid;
AS_36_link_valid(L5PHIBn1) <= d(43).valid;
AS_36_link_valid(L5PHICn1) <= d(43).valid;
AS_36_link_valid(L5PHIDn1) <= d(42).valid;
AS_36_link_valid(L6PHIAn1) <= d(42).valid;
AS_36_link_valid(L6PHIBn1) <= d(41).valid;
AS_36_link_valid(L6PHICn1) <= d(40).valid;
AS_36_link_valid(L6PHIDn1) <= d(40).valid;
AS_36_link_valid(D1PHIAn1) <= d(39).valid;
AS_36_link_valid(D1PHIBn1) <= d(39).valid;
AS_36_link_valid(D1PHICn1) <= d(38).valid;
AS_36_link_valid(D1PHIDn1) <= d(38).valid;
AS_36_link_valid(D2PHIAn1) <= d(37).valid;
AS_36_link_valid(D2PHIBn1) <= d(36).valid;
AS_36_link_valid(D2PHICn1) <= d(36).valid;
AS_36_link_valid(D2PHIDn1) <= d(35).valid;
AS_36_link_valid(D3PHIAn1) <= d(35).valid;
AS_36_link_valid(D3PHIBn1) <= d(34).valid;
AS_36_link_valid(D3PHICn1) <= d(34).valid;
AS_36_link_valid(D3PHIDn1) <= d(33).valid;
AS_36_link_valid(D4PHIAn1) <= d(32).valid;
AS_36_link_valid(D4PHIBn1) <= d(32).valid;
AS_36_link_valid(D4PHICn1) <= d(31).valid;
AS_36_link_valid(D4PHIDn1) <= d(31).valid;
AS_36_link_valid(D5PHIAn1) <= d(30).valid;
AS_36_link_valid(D5PHIBn1) <= d(29).valid;
AS_36_link_valid(D5PHICn1) <= d(29).valid;
AS_36_link_valid(D5PHIDn1) <= d(28).valid;

MPAR_73_link_data(L1L2ABC) <= MTPAR_signals(75 downto 0);
MPAR_73_link_data(L1L2DE) <= MTPAR_signals(151 downto 76);
MPAR_73_link_data(L1L2F) <= MTPAR_signals(227 downto 152);
Expand All @@ -165,7 +214,25 @@ begin
MPAR_73_link_data(L1D1EFGH) <= MTPAR_signals(1063 downto 988);
MPAR_73_link_data(L2D1ABCD) <= MTPAR_signals(1139 downto 1064);

--for now assume valid bit on all links is identical, may need to add "when d(#).valid" on many above lines to latch if valid is not universal
valid <= d(9).valid;
MPAR_73_link_valid(L1L2ABC) <= d(27).valid;
MPAR_73_link_valid(L1L2DE) <= d(26).valid;
MPAR_73_link_valid(L1L2F) <= d(25).valid;
MPAR_73_link_valid(L1L2G) <= d(24).valid;
MPAR_73_link_valid(L1L2HI) <= d(23).valid;
MPAR_73_link_valid(L1L2JKL) <= d(22).valid;
MPAR_73_link_valid(L2L3ABCD) <= d(20).valid;
MPAR_73_link_valid(L3L4AB) <= d(19).valid;
MPAR_73_link_valid(L3L4CD) <= d(18).valid;
MPAR_73_link_valid(L5L6ABCD) <= d(17).valid;
MPAR_73_link_valid(D1D2ABCD) <= d(16).valid;
MPAR_73_link_valid(D3D4ABCD) <= d(14).valid;
MPAR_73_link_valid(L1D1ABCD) <= d(13).valid;
MPAR_73_link_valid(L1D1EFGH) <= d(12).valid;
MPAR_73_link_valid(L2D1ABCD) <= d(11).valid;

--latch bx_link_data when not valid
bx_link_data_int <= d(9).data(2 downto 0) when (d(9).valid='1') else bx_link_data_int;
bx_link_data <= bx_link_data_int;
bx_link_valid <= d(9).valid;

end rtl;
94 changes: 50 additions & 44 deletions IntegrationTests/DualFPGA/firmware/hdl/payload_f2.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -46,27 +46,29 @@ end emp_payload;

architecture rtl of emp_payload is

signal AS_36_link_data : t_arr_AS_36_37b;
signal MPAR_73_link_data : t_arr_MTPAR_73_76b;
signal bx_link_data : std_logic_vector(2 downto 0);
signal link_data_valid : std_logic;
signal PC_start : std_logic;
signal PC_bx_in : std_logic_vector(2 downto 0);
signal AS_36_wea : t_arr_AS_36_1b;
signal AS_36_writeaddr : t_arr_AS_36_ADDR;
signal AS_36_din : t_arr_AS_36_DATA;
signal MPAR_73_wea : t_arr_MTPAR_73_1b;
signal MPAR_73_writeaddr : t_arr_MTPAR_73_ADDR;
signal MPAR_73_din : t_arr_MTPAR_73_DATA;
signal s_tftokf : t_channlesTB(numTW_104 - 1 downto 0);
signal s_kfin : t_channlesTB(numNodesKF - 1 downto 0);
signal s_kfout : t_frames(numLinksTFP - 1 downto 0);
signal s_tfout : ldata(numLinksTFP - 1 downto 0);
signal FT_bx_out_0 : std_logic_vector(2 downto 0);
signal FT_bx_out_vld : std_logic;
signal FT_done : std_logic;
signal FT_last_track : std_logic;
signal FT_last_track_vld : std_logic;
signal AS_36_link_data : t_arr_AS_36_37b;
signal MPAR_73_link_data : t_arr_MTPAR_73_76b;
signal AS_36_link_valid : t_arr_AS_36_1b;
signal MPAR_73_link_valid : t_arr_MTPAR_73_1b;
signal bx_link_data : std_logic_vector(2 downto 0);
signal bx_link_valid : std_logic;
signal PC_start : std_logic;
signal PC_bx_in : std_logic_vector(2 downto 0);
signal AS_36_wea : t_arr_AS_36_1b;
signal AS_36_writeaddr : t_arr_AS_36_ADDR;
signal AS_36_din : t_arr_AS_36_DATA;
signal MPAR_73_wea : t_arr_MTPAR_73_1b;
signal MPAR_73_writeaddr : t_arr_MTPAR_73_ADDR;
signal MPAR_73_din : t_arr_MTPAR_73_DATA;
signal s_tftokf : t_channlesTB(numTW_104 - 1 downto 0);
signal s_kfin : t_channlesTB(numNodesKF - 1 downto 0);
signal s_kfout : t_frames(numLinksTFP - 1 downto 0);
signal s_tfout : ldata(numLinksTFP - 1 downto 0);
signal FT_bx_out_0 : std_logic_vector(2 downto 0);
signal FT_bx_out_vld : std_logic;
signal FT_done : std_logic;
signal FT_last_track : std_logic;
signal FT_last_track_vld : std_logic;
signal TW_104_stream_AV_din : t_arr_TW_104_DATA;
signal TW_104_stream_A_write : t_arr_TW_104_1b;
signal DW_49_stream_AV_din : t_arr_DW_49_DATA;
Expand All @@ -81,34 +83,38 @@ begin
-----------------------------------------------------------------------------
linktosecproc2_1 : entity work.linktosecproc2
port map (
clk => clk_p,
rst => rst,
d => d,
AS_36_link_data => AS_36_link_data,
MPAR_73_link_data => MPAR_73_link_data,
bx_link_data => bx_link_data,
valid => link_data_valid
clk => clk_p,
rst => rst,
d => d,
AS_36_link_data => AS_36_link_data,
MPAR_73_link_data => MPAR_73_link_data,
bx_link_data => bx_link_data,
AS_36_link_valid => AS_36_link_valid,
MPAR_73_link_valid => MPAR_73_link_valid,
bx_link_valid => bx_link_valid
);

-----------------------------------------------------------------------------
-- Drive memory writes for SectorProcessor
-----------------------------------------------------------------------------
sp2_mem_writer_1 : entity work.sp2_mem_writer
port map (
clk => clk_p,
reset => rst,
bx_link_data => bx_link_data,
AS_36_link_data => AS_36_link_data,
MPAR_73_link_data => MPAR_73_link_data,
link_data_valid => link_data_valid,
AS_36_wea => AS_36_wea,
AS_36_writeaddr => AS_36_writeaddr,
AS_36_din => AS_36_din,
MPAR_73_wea => MPAR_73_wea,
MPAR_73_writeaddr => MPAR_73_writeaddr,
MPAR_73_din => MPAR_73_din,
PC_start => PC_start,
PC_bx_in => PC_bx_in
clk => clk_p,
reset => rst,
AS_36_link_data => AS_36_link_data,
MPAR_73_link_data => MPAR_73_link_data,
bx_link_data => bx_link_data,
AS_36_link_valid => AS_36_link_valid,
MPAR_73_link_valid => MPAR_73_link_valid,
bx_link_valid => bx_link_valid,
AS_36_wea => AS_36_wea,
AS_36_writeaddr => AS_36_writeaddr,
AS_36_din => AS_36_din,
MPAR_73_wea => MPAR_73_wea,
MPAR_73_writeaddr => MPAR_73_writeaddr,
MPAR_73_din => MPAR_73_din,
PC_start => PC_start,
PC_bx_in => PC_bx_in
);

-----------------------------------------------------------------------------
Expand Down Expand Up @@ -192,7 +198,7 @@ begin
out_dout => s_tfout
);

q(108) <= s_tfout(0);
q(109) <= s_tfout(1);
q(92) <= s_tfout(0);
q(93) <= s_tfout(1);

end rtl;
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