fix typos

_typos.toml

@@ -0,0 +1,9 @@
+# Typo check: https://github.com/crate-ci/typos
+
+[files]
+extend-exclude = ["go.mod", "go.sum", "fuzz/go.mod", "fuzz/go.sum"]
+
+[default.extend-words]
+Pn = "Pn"
+worl = "worl"
+rcall = "rcall"

internal/atm/pgen/pgen_amd64.go

@@ -383,7 +383,7 @@ func (self *CodeGen) Generate(s hir.Program, sp uintptr) *Func {
 		self.translate(p, v)
 	}
 
-	/* generate all defered blocks */
+	/* generate all deferred blocks */
 	for _, fp := range self.defs {
 		p.Link(fp.ref)
 		fp.def(p)
@@ -581,7 +581,7 @@ func (self *CodeGen) ref(s string) *x86_64.Label {
 	var k bool
 	var p *x86_64.Label
 
-	/* check for existance */
+	/* check for existence */
 	if p, k = self.jmps[s]; k {
 		return p
 	}

internal/atm/ssa/builder.go

@@ -75,12 +75,12 @@ func (self *_GraphBuilder) build(p hir.Program) *CFG {
 	ret.Root = ret.CreateBlock()
 	ret.Root.Ins = make([]IrNode, 0, len(_GenericRegs)+len(_PointerRegs)+N_size)
 
-	/* implicit defination of all generic registers */
+	/* implicit definition of all generic registers */
 	for _, v := range _GenericRegs {
 		ret.Root.Ins = append(ret.Root.Ins, &IrConstInt{R: Rv(v), V: 0})
 	}
 
-	/* implicit defination of all pointer registers */
+	/* implicit definition of all pointer registers */
 	for _, v := range _PointerRegs {
 		ret.Root.Ins = append(ret.Root.Ins, &IrConstPtr{R: Rv(v), P: nil, M: Volatile})
 	}

internal/atm/ssa/pass_branchelim.go

@@ -411,7 +411,7 @@ func (self *_Proof) verifyCorrectness() bool {
 			}
 		}
 
-		/* expand all the definations */
+		/* expand all the definitions */
 		for _, v := range sp {
 			if p, ok := v.rhs.(_Stmt); ok {
 				if r, rk := rr.at(v.lhs); rk {

internal/atm/ssa/pass_comsubexpr.go

@@ -118,14 +118,14 @@ func (self *_VidMap) define(vid string, reg Reg) {
 	self.m[vid] = reg
 }
 
-// CSE performs the Common Sub-expression Elimintation optimization.
+// CSE performs the Common Sub-expression Elimination optimization.
 type CSE struct{}
 
 func (self CSE) dfs(cfg *CFG, bb *BasicBlock, vm *_VidMap) {
 	ins := bb.Ins
 	vals := vm.derive()
 
-	/* scan every instructions */
+	/* scan every instruction */
 	for i, v := range ins {
 		var r Reg
 		var d _Vid
@@ -151,7 +151,7 @@ func (self CSE) dfs(cfg *CFG, bb *BasicBlock, vm *_VidMap) {
 				continue
 			}
 
-			/* add to definations if not found */
+			/* add to definitions if not found */
 			if !ok {
 				vals.define(vid, *s)
 				continue
@@ -167,7 +167,7 @@ func (self CSE) dfs(cfg *CFG, bb *BasicBlock, vm *_VidMap) {
 			*s = s.Zero()
 		}
 
-		/* all the definations are been replaced */
+		/* all the definitions are been replaced */
 		if repc == i+len(defs) {
 			bb.Ins = append(bb.Ins[:i], bb.Ins[i+1:]...)
 		}

internal/atm/ssa/pass_phiprop.go

@@ -44,7 +44,7 @@ func (self PhiProp) dfs(dag *simple.DirectedGraph, bb *BasicBlock, vis map[int]*
 	vis[bb.Id] = bb
 	path[bb.Id] = struct{}{}
 
-	/* traverse all the sucessors */
+	/* traverse all the successors */
 	for it := bb.Term.Successors(); it.Next(); {
 		v := it.Block()
 		s, d := bb.Id, v.Id
@@ -142,7 +142,7 @@ func (self PhiProp) Apply(cfg *CFG) {
 			var ps float64
 			var pp float64
 
-			/* find the branch with the hightest probability */
+			/* find the branch with the highest probability */
 			for b, r := range p.V {
 				if pp = weight[b.Id][bb.Id]; ps < pp {
 					rs = *r

internal/atm/ssa/pass_regalloc.go

@@ -272,7 +272,7 @@ func (self RegAlloc) colorDiffWithReload(rig *simple.UndirectedGraph, reg Reg, r
 		colors[i] = struct{}{}
 	}
 
-	/* choose a different color from it's neightbors */
+	/* choose a different color from it's neighbors */
 	for r := rig.From(int64(reg)); r.Next(); {
 		delete(colors, colormap[Reg(r.Node().ID())])
 	}
@@ -299,7 +299,7 @@ func (self RegAlloc) colorSameWithReg(rig *simple.UndirectedGraph, reloadReg Reg
 		colors[i] = struct{}{}
 	}
 
-	/* choose a different color from it's neightbors */
+	/* choose a different color from it's neighbors */
 	for r := rig.From(int64(reloadReg)); r.Next(); {
 		delete(colors, colormap[Reg(r.Node().ID())])
 	}
@@ -326,7 +326,7 @@ func (self RegAlloc) Apply(cfg *CFG) {
 	coalescemap := make(map[Reg]Reg)
 	invcoalescemap := make(map[Reg][]Reg)
 
-	/* register coalescer */
+	/* register coalesce */
 	coalesce := func(rr []*Reg) {
 		for _, r := range rr {
 			if c, ok := coalescemap[*r]; ok {
@@ -554,7 +554,7 @@ func (self RegAlloc) Apply(cfg *CFG) {
 			}
 		})
 
-		/* try again if coalesce occured */
+		/* try again if coalesce occurred */
 		if len(coalescemap) != 0 {
 			continue
 		}

internal/atm/ssa/pass_splitcritical.go

@@ -45,7 +45,7 @@ func (SplitCritical) Apply(cfg *CFG) {
 					nb++
 				}
 
-				/* the predecessor have more than 1 successors, this is a critcal edge */
+				/* the predecessor have more than 1 successor, this is a critical edge */
 				if nb > 1 {
 					edges = append(edges, _CrEdge{
 						to:   bb,

internal/atm/ssa/pass_stack_liveness.go

@@ -64,7 +64,7 @@ func (self StackLiveness) livein(lr map[Pos]SlotSet, bb *BasicBlock, in map[int]
 				panic("stackmap: invalid spill Op")
 			}
 
-		/* store operaion marks the value is alive since here */
+		/* store operation marks the value is alive since here */
 		case IrSpillStore:
 			{
 				if sl.remove(sp.S) {
@@ -74,7 +74,7 @@ func (self StackLiveness) livein(lr map[Pos]SlotSet, bb *BasicBlock, in map[int]
 				}
 			}
 
-		/* load operaion marks the value is alive until here */
+		/* load operation marks the value is alive until here */
 		case IrSpillReload:
 			{
 				if sl.add(sp.S) {

internal/atm/ssa/pass_tdce.go

@@ -24,19 +24,19 @@ func (TDCE) Apply(cfg *CFG) {
 		done := true
 		decl := make(map[Reg]struct{})
 
-		/* Phase 1: Mark all the definations */
+		/* Phase 1: Mark all the definitions */
 		cfg.PostOrder().ForEach(func(bb *BasicBlock) {
 			var ok bool
 			var defs IrDefinitions
 
-			/* mark all definations in Phi nodes */
+			/* mark all definitions in Phi nodes */
 			for _, v := range bb.Phi {
 				for _, r := range v.Definitions() {
 					decl[*r] = struct{}{}
 				}
 			}
 
-			/* mark all definations in instructions if any */
+			/* mark all definitions in instructions if any */
 			for _, v := range bb.Ins {
 				if defs, ok = v.(IrDefinitions); ok {
 					for _, r := range defs.Definitions() {
@@ -45,7 +45,7 @@ func (TDCE) Apply(cfg *CFG) {
 				}
 			}
 
-			/* mark all definations in terminators if any */
+			/* mark all definitions in terminators if any */
 			if defs, ok = bb.Term.(IrDefinitions); ok {
 				for _, r := range defs.Definitions() {
 					decl[*r] = struct{}{}
@@ -87,7 +87,7 @@ func (TDCE) Apply(cfg *CFG) {
 			var ok bool
 			var defs IrDefinitions
 
-			/* replace unused Phi assigments with zero registers */
+			/* replace unused Phi assignments with zero registers */
 			for _, v := range bb.Phi {
 				for _, r := range v.Definitions() {
 					if _, ok = decl[*r]; ok && r.Kind() != K_zero {
@@ -96,7 +96,7 @@ func (TDCE) Apply(cfg *CFG) {
 				}
 			}
 
-			/* replace unused instruction assigments with zero registers */
+			/* replace unused instruction assignments with zero registers */
 			for _, v := range bb.Ins {
 				if defs, ok = v.(IrDefinitions); ok {
 					for _, r := range defs.Definitions() {
@@ -107,7 +107,7 @@ func (TDCE) Apply(cfg *CFG) {
 				}
 			}
 
-			/* replace unused terminator assigments with zero registers */
+			/* replace unused terminator assignments with zero registers */
 			if defs, ok = bb.Term.(IrDefinitions); ok {
 				for _, r := range defs.Definitions() {
 					if _, ok = decl[*r]; ok && r.Kind() != K_zero {
@@ -117,7 +117,7 @@ func (TDCE) Apply(cfg *CFG) {
 			}
 		})
 
-		/* Phase 4: Remove the entire defination if it's all zeros */
+		/* Phase 4: Remove the entire definition if it's all zeros */
 		cfg.PostOrder().ForEach(func(bb *BasicBlock) {
 			phi, ins := bb.Phi, bb.Ins
 			bb.Phi, bb.Ins = bb.Phi[:0], bb.Ins[:0]

internal/atm/ssa/phi.go

@@ -68,12 +68,12 @@ func insertPhiNodes(cfg *CFG) {
 		}
 	}
 
-	/* find out all the variable defination sites */
+	/* find out all the variable definition sites */
 	for q.Enqueue(cfg.Root); !q.Empty(); {
 		p := q.Dequeue().(*BasicBlock)
 		addImmediateDominated(cfg.DominatorOf, p, q)
 
-		/* mark all the defination sites */
+		/* mark all the definition sites */
 		for def := range orig[p.Id] {
 			defs[def] = appendBlock(defs[def], p)
 		}

internal/atm/ssa/rename.go

@@ -107,7 +107,7 @@ func (self _Renamer) renameblock(cfg *CFG, bb *BasicBlock) {
 		self.renameblock(cfg, p)
 	}
 
-	/* pop the definations */
+	/* pop the definitions */
 	for _, s := range d {
 		self.popr(s)
 	}
@@ -147,7 +147,7 @@ func normalizeRegisters(cfg *CFG) {
 	q := lane.NewQueue()
 	r := make(map[Reg]Reg)
 
-	/* find all the register definations */
+	/* find all the register definitions */
 	for q.Enqueue(cfg.Root); !q.Empty(); {
 		p := q.Dequeue().(*BasicBlock)
 		addImmediateDominated(cfg.DominatorOf, p, q)

internal/binary/encoder/compiler_encode.go

@@ -292,7 +292,7 @@ func (self *Compiler) compileStructField(p *Program, sp int, fv defs.Field, star
 			self.compileStructRequired(p, sp, fv, startpc)
 		}
 
-	/* sequencial types */
+	/* sequential types */
 	case defs.T_map:
 		fallthrough
 	case defs.T_set:

internal/binary/encoder/compiler_measure.go

@@ -286,7 +286,7 @@ func (self *Compiler) measureField(p *Program, sp int, fv defs.Field, startpc in
 			self.measureStructRequired(p, sp, fv, startpc)
 		}
 
-	/* sequencial types */
+	/* sequential types */
 	case defs.T_map:
 		fallthrough
 	case defs.T_set:

internal/binary/encoder/optimizer.go

@@ -400,7 +400,7 @@ func _PASS_SizeCheckMerging(bb *BasicBlock) {
 	}
 }
 
-// Literal Merging Pass: merges all consectutive byte, word or long instructions.
+// Literal Merging Pass: merges all consecutive byte, word or long instructions.
 func _PASS_LiteralMerging(bb *BasicBlock) {
 	p := bb.P
 	i := bb.Src