Correctly simulate passed time before first clock edge in verilator #50
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martijnbastiaan
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`9.2` barely works with clash `9.4.8` has the slow start problem
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The FFI code used a default of 50 nanoseconds as time passed before the first clock edge. This resulted in an unobservable reset pulse when used with `resetGenN d1` because verilator's simulation time is off by a factor 1000. Now derive the time before the clock edge as a single period of vexrisc clock domain.
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The FFI code used a default of 50 nanoseconds as time passed before the first clock edge. This resulted in an unobservable reset pulse when used with
resetGenN d1because verilator's simulation time is off by a factor 1000.Now derive the time before the clock edge as a single period of vexrisc clock domain.