add JTAG support to the core

.github/workflows/ci.yml

@@ -131,7 +131,7 @@ jobs:
         uses: actions/cache@v3
         with:
           path: |
-            ~/.cabal/store
+            ~/.local/state/cabal/store/
           key: packages-cachebust-2-${{ matrix.ghc }}-${{ hashFiles('cabal.project.freeze', 'cabal.project') }}
           restore-keys: packages-cachebust-2-${{ matrix.ghc }}
 
@@ -172,6 +172,10 @@ jobs:
         with:
           name: vexriscv-test-binaries
 
+      - name: Work around dubious owner error
+        run: |
+          git config --global --add safe.directory "$(pwd)"
+
       - name: Extract VexRiscv Integration Tests
         run: |
           tar -x -f vexriscv-test-binaries.tar
@@ -183,3 +187,7 @@ jobs:
       - name: Run `clash-vexriscv-sim` unittests
         run: |
           cabal run clash-vexriscv-sim:unittests
+
+      - name: Run `clash-vexriscv-sim` HDL test
+        run: |
+          cabal run clash-vexriscv-sim:hdl-test

.gitignore

@@ -65,3 +65,9 @@ log
 vivado_*
 tight_setup_hold_pins.txt
 .Xil
+
+# Verilator debug output
+simulation_dump.vcd
+
+# Clash output
+verilog

Cargo.toml

@@ -13,5 +13,6 @@ opt-level = "z"
 [workspace]
 members = [
   "clash-vexriscv-sim/test-programs",
+  "debug-test",
 ]
 resolver = "2"

cabal.project

@@ -7,7 +7,6 @@ packages:
   clash-vexriscv-sim/
 
 write-ghc-environment-files: always
-
 tests: True
 
 

clash-vexriscv-sim/app/HdlTest.hs

@@ -1,21 +1,10 @@
--- SPDX-FileCopyrightText: 2023 Google LLC
+-- SPDX-FileCopyrightText: 2023-2024 Google LLC
 --
 -- SPDX-License-Identifier: Apache-2.0
 
-import Clash.Prelude
-import Clash.Annotations.TH
+import Prelude
 
-import VexRiscv
-
-circuit ::
-  "CLK" ::: Clock System ->
-  "RST" ::: Reset System ->
-  "INPUT" ::: Signal System Input ->
-  "OUTPUT" ::: Signal System Output
-circuit clk rst input =
-  withClockResetEnable clk rst enableGen vexRiscv input
-
-makeTopEntity 'circuit
+import qualified Clash.Main as Clash
 
 main :: IO ()
-main = pure ()
+main = Clash.defaultMain ["Utils.Instance", "-main-is", "circuit", "--verilog"]

clash-vexriscv-sim/app/VexRiscvSimulation.hs

@@ -1,14 +1,16 @@
--- SPDX-FileCopyrightText: 2022 Google LLC
+-- SPDX-FileCopyrightText: 2022-2024 Google LLC
 --
 -- SPDX-License-Identifier: Apache-2.0
 {-# LANGUAGE NumericUnderscores #-}
 {-# LANGUAGE MultiWayIf #-}
 {-# LANGUAGE GADTs #-}
 
+{-# OPTIONS_GHC -fconstraint-solver-iterations=10 #-}
+
 import Clash.Prelude
 
 import Protocols.Wishbone
-import VexRiscv (Output(iBusWbM2S, dBusWbM2S))
+import VexRiscv (CpuOut(iBusWbM2S, dBusWbM2S))
 
 import qualified Data.List as L
 
@@ -20,8 +22,9 @@ import System.IO (putChar, hFlush, stdout)
 import Text.Printf (printf)
 
 
-import Utils.ProgramLoad (loadProgram)
+import Utils.ProgramLoad (loadProgramDmem)
 import Utils.Cpu (cpu)
+import System.Exit (exitFailure)
 
 --------------------------------------
 --
@@ -59,9 +62,9 @@ debugConfig =
 --
 {-
   InspectBusses
-    50
     0
-    (Just 300)
+    0
+    (Just 100)
     True
     True
 -- -}
@@ -75,39 +78,53 @@ main = do
 
   (iMem, dMem) <-
     withClockResetEnable @System clockGen resetGen enableGen $
-      loadProgram @System elfFile
+      loadProgramDmem @System elfFile
 
-  let cpuOut@(unbundle -> (_circuit, writes, iBus, dBus)) =
+  let cpuOut@(unbundle -> (_circuit, writes, _iBus, _dBus)) =
         withClockResetEnable @System clockGen (resetGenN (SNat @2)) enableGen $
-          bundle (cpu iMem dMem)
+          let (circ, writes1, iBus, dBus) = cpu (Just 7894) iMem dMem
+              dBus' = register emptyWishboneS2M dBus
+          in bundle (circ, writes1, iBus, dBus')
 
   case debugConfig of
     RunCharacterDevice ->
-      forM_ (sample_lazy @System (bundle (dBus, iBus, writes))) $ \(dS2M, iS2M, write) -> do
-        when (err dS2M) $
-          putStrLn "D-bus ERR reply"
+      forM_ (sample_lazy @System (bundle (register @System (unpack 0) cpuOut, cpuOut))) $
+        \((_out, write, dS2M, iS2M), (out1, _write, _dS2M, _iS2M)) -> do
+
+        when (err dS2M) $ do
+          let dBusM2S = dBusWbM2S out1
+          let dAddr = toInteger (addr dBusM2S) -- `shiftL` 2
+          printf "D-bus ERR reply % 8X (% 8X)\n" (toInteger $ dAddr `shiftL` 2) (toInteger dAddr)
+          exitFailure
+
+        when (err iS2M) $ do
+          let iBusM2S = iBusWbM2S out1
+          let iAddr = toInteger (addr iBusM2S) -- `shiftL` 2
+          printf "I-bus ERR reply % 8X (% 8X)\n" (toInteger $ iAddr `shiftL` 2) (toInteger iAddr)
+          printf "%s\n" (showX iBusM2S)
+          exitFailure
 
-        when (err iS2M) $
-          putStrLn "I-bus ERR reply"
-
         case write of
           Just (address, value) | address == 0x0000_1000 -> do
             let (_ :: BitVector 24, b :: BitVector 8) = unpack value
             putChar $ chr (fromEnum b)
             hFlush stdout
+            pure ()
           _ -> pure ()
       -- performPrintsToStdout 0x0000_1000 (sample_lazy $ bitCoerce <$> writes)
     InspectBusses initCycles uninteresting interesting iEnabled dEnabled -> do
-      
+
       let skipTotal = initCycles + uninteresting
 
       let sampled = case interesting of
             Nothing -> L.zip [0 ..] $ sample_lazy @System cpuOut
             Just nInteresting ->
-              let total = initCycles + uninteresting + nInteresting in L.zip [0 ..] $ L.take total $ sample_lazy @System cpuOut
+              let total = initCycles + uninteresting + nInteresting in
+              L.zip [0 ..] $ L.take total $ sample_lazy @System cpuOut
 
       forM_ sampled $ \(i, (out, _, iBusS2M, dBusS2M)) -> do
-        let doPrint = i >= skipTotal
+        let
+          doPrint = i >= skipTotal
 
         -- I-bus interactions
 
@@ -143,6 +160,9 @@ main = do
               <> ")"
           putStrLn $ "            - iS2M: " <> iResp <> " - " <> iRespData
 
+        when (err iBusS2M)
+          exitFailure
+
         -- D-bus interactions
 
         when (doPrint && dEnabled) $ do
@@ -192,6 +212,9 @@ main = do
                 <> writeDat
                 <> "> - "
             putStrLn $ "dS2M: " <> dResp <> dRespData
+
+        when (err dBusS2M)
+          exitFailure
     InspectWrites ->
       forM_ (catMaybes $ sample_lazy @System writes) $ \(address, value) -> do
         printf "W: % 8X <- % 8X\n" (toInteger address) (toInteger value)

clash-vexriscv-sim/clash-vexriscv-sim.cabal

@@ -7,6 +7,9 @@ author:              QBayLogic B.V.
 maintainer:          [email protected]
 Copyright:           Copyright © 2022 Google LLC
 
+extra-source-files:
+  data/*.cfg
+
 common common-options
   default-extensions:
     BangPatterns
@@ -43,6 +46,13 @@ common common-options
 
     -- Prelude isn't imported by default as Clash offers Clash.Prelude
     NoImplicitPrelude
+
+  -- See https://github.com/clash-lang/clash-compiler/pull/2511
+  if impl(ghc >= 9.4)
+    CPP-Options: -DCLASH_OPAQUE=OPAQUE
+  else
+    CPP-Options: -DCLASH_OPAQUE=NOINLINE
+
   ghc-options:
     -Wall -Wcompat
 
@@ -73,6 +83,7 @@ library
   default-language: Haskell2010
   exposed-modules:
     Utils.Cpu
+    Utils.Instance
     Utils.Interconnect
     Utils.ProgramLoad
     Utils.ReadElf
@@ -85,26 +96,21 @@ library
     clash-vexriscv,
     elf >= 0.31 && < 0.32,
 
-executable clash
-  import: common-options
-  main-is: app/Clash.hs
-  build-Depends: base, clash-ghc
-
+-- XXX: Doesn't really belong in clash-vexriscv-SIM
 executable hdl-test
   import: common-options
   main-is: app/HdlTest.hs
   build-Depends:
     base,
-    clash-prelude,
-    clash-protocols,
-    clash-vexriscv,
+    clash-ghc,
     clash-vexriscv-sim,
 
 executable clash-vexriscv-bin
   import: common-options
   main-is: VexRiscvSimulation.hs
   hs-source-dirs: app
   default-language: Haskell2010
+  ghc-options: -threaded -rtsopts "-with-rtsopts=-M100M"
   build-depends:
     base,
     clash-prelude,
@@ -122,18 +128,28 @@ test-suite unittests
   type: exitcode-stdio-1.0
   -- TODO: enable parallel tests:
   -- ghc-options: -threaded -rtsopts -with-rtsopts=-N
+  build-tool-depends:
+    clash-vexriscv-sim:clash-vexriscv-bin
+  autogen-modules:
+    Paths_clash_vexriscv_sim
   ghc-options: -threaded
   main-is: tests.hs
+  other-modules:
+    Paths_clash_vexriscv_sim
+    Tests.Jtag
   build-depends:
+    async,
     base,
+    bytestring,
     clash-prelude,
     clash-protocols,
-    clash-vexriscv,
     clash-vexriscv-sim,
-    bytestring,
+    clash-vexriscv,
     containers,
     directory,
-    temporary >=1.1 && <1.4,
+    extra,
+    filepath,
+    process,
     tasty >= 1.2 && < 1.6,
     tasty-hunit >= 0.10 && < 0.11,
-    filepath
+    temporary >=1.1 && <1.4,

clash-vexriscv-sim/data/vexriscv_gdb.cfg

@@ -0,0 +1,45 @@
+# Execute using:
+#
+#   gdb --command vexriscv_gdb.cfg
+#
+
+# SPDX-FileCopyrightText: 2024 Google LLC
+#
+# SPDX-License-Identifier: CC0-1.0
+
+# Assume "print_a" is running on the CPU
+file "target/riscv32imc-unknown-none-elf/debug/print_a"
+
+# Work around issues where simulation is too slow to respond to keep-alive messages,
+# confusing either OpenOCD or GDB. Note that it will still complain about "missed"
+# deadlines, but it won't fail..
+set remotetimeout unlimited
+
+# Connect to OpenOCD
+target extended-remote :3333
+
+# List registers
+i r
+
+# break on main function entrance
+break main
+
+# Jump to start address, should run until it hits main
+jump _start
+
+# Run until we hit function "done", meaning it should have printed "a"
+disable 1
+break print_a::done
+continue
+disable 2
+
+# Load program
+file "target/riscv32imc-unknown-none-elf/debug/print_b"
+load
+
+# Jump to start address. Should now output "b".
+break print_b::done
+jump _start
+
+# Stop running GDB
+quit