Connect JTAG reset out to CPU reset in, in cpu

clash-vexriscv-sim/clash-vexriscv-sim.cabal

@@ -7,6 +7,9 @@ author:              QBayLogic B.V.
 maintainer:          [email protected]
 Copyright:           Copyright © 2022 Google LLC
 
+extra-source-files:
+  data/*.cfg
+
 common common-options
   default-extensions:
     BangPatterns
@@ -125,9 +128,12 @@ test-suite unittests
   -- ghc-options: -threaded -rtsopts -with-rtsopts=-N
   build-tool-depends:
     clash-vexriscv-sim:clash-vexriscv-bin
+  autogen-modules:
+    Paths_clash_vexriscv_sim
   ghc-options: -threaded
   main-is: tests.hs
   other-modules:
+    Paths_clash_vexriscv_sim
     Tests.Jtag
   build-depends:
     async,

clash-vexriscv-sim/src/Utils/Cpu.hs

@@ -21,6 +21,7 @@ import GHC.Stack (HasCallStack)
 
 import Utils.ProgramLoad (Memory, DMemory)
 import Utils.Interconnect (interconnectTwo)
+import Clash.Explicit.Prelude (unsafeOrReset)
 
 createDomain vXilinxSystem{vName="Basic50", vPeriod= hzToPeriod 50_000_000}
 
@@ -32,7 +33,12 @@ Address space
 0b0100 0x4000_0000 data memory
 -}
 cpu ::
-  (HasCallStack, HiddenClockResetEnable dom) =>
+  ( HasCallStack
+  , HiddenClockResetEnable dom
+  -- XXX: VexRiscv responds asynchronously to the reset signal. Figure out how
+  --      convenient it is to use this within a design with synchronous resets.
+  -- , HasAsynchronousReset dom
+  ) =>
   Maybe Integer ->
   DMemory dom ->
   DMemory dom ->
@@ -51,7 +57,11 @@ cpu jtagPort bootIMem bootDMem =
   , dS2M
   )
   where
-    (output, jtagOut) = vexRiscv hasClock hasReset input jtagIn
+    (output, jtagOut) = vexRiscv hasClock (hasReset `unsafeOrReset` jtagReset) input jtagIn
+
+    jtagReset =
+      unsafeFromActiveHigh $ register False $
+        bitToBool . debugReset <$> jtagOut
 
     jtagIn = case jtagPort of
       Just port -> vexrJtagBridge (fromInteger port) jtagOut

clash-vexriscv-sim/tests/Tests/Jtag.hs

@@ -13,6 +13,8 @@ import System.Process
 import Test.Tasty
 import Test.Tasty.HUnit
 
+import Paths_clash_vexriscv_sim (getDataFileName)
+
 cabalListBin :: String -> IO FilePath
 cabalListBin name = do
   trim <$> readProcess "cabal" ["-v0", "list-bin", name] ""
@@ -27,10 +29,10 @@ getPrintElfPath :: IO FilePath
 getPrintElfPath = pure "target/riscv32imc-unknown-none-elf/debug/print_a"
 
 getOpenOcdCfgPath :: IO FilePath
-getOpenOcdCfgPath = pure "vexriscv_sim.cfg"
+getOpenOcdCfgPath = getDataFileName "data/vexriscv_sim.cfg"
 
 getGdbCmdPath :: IO FilePath
-getGdbCmdPath = pure "vexriscv_gdb.cfg"
+getGdbCmdPath = getDataFileName "data/vexriscv_gdb.cfg"
 
 expectLine :: Handle -> String -> Assertion
 expectLine h expected = do
@@ -47,6 +49,12 @@ waitForLine h expected = do
     then pure ()
     else waitForLine h expected
 
+-- | Run three processes in parallel:
+--
+-- 1. The VexRiscv simulation. It opens a TCP socket for OpenOCD to connect to.
+-- 2. OpenOCD. It connects to the VexRiscv simulation and exposes a GDB server.
+-- 3. GDB. It connects to the OpenOCD GDB server and bunch of commands.
+--
 test :: Assertion
 test = do
   simulateExecPath <- getSimulateExecPath
@@ -67,8 +75,8 @@ test = do
     }
 
     gdbProc = (proc "gdb" ["--command", gdbCmdPath]){
-        std_out = CreatePipe -- Comment this line to see GDB output
-      , cwd = Just projectRoot
+      std_out = CreatePipe, -- Comment this line to see GDB output
+      cwd = Just projectRoot
     }
 
   withCreateProcess vexRiscvProc $ \_ (fromJust -> vexRiscvStdOut) _ _ -> do
@@ -77,6 +85,7 @@ test = do
 
     -- CPU has started, so we can start OpenOCD
     withCreateProcess openOcdProc $ \_ _ (fromJust -> openOcdStdErr) _ -> do
+      hSetBuffering openOcdStdErr LineBuffering
       waitForLine openOcdStdErr "Halting processor"
 
       -- OpenOCD has started, so we can start GDB