Added HDL generation test

Tests the bare minimum: whether HDL can be generated using Clash

.github/workflows/ci.yml

@@ -183,3 +183,7 @@ jobs:
       - name: Run `clash-vexriscv-sim` unittests
         run: |
           cabal run clash-vexriscv-sim:unittests
+
+      - name: Run `clash-vexriscv-sim` HDL test
+        run: |
+          cabal run clash-vexriscv-sim:hdl-test

.gitignore

@@ -68,3 +68,6 @@ tight_setup_hold_pins.txt
 
 # Verilator debug output
 simulation_dump.vcd
+
+# Clash output
+verilog

clash-vexriscv-sim/app/HdlTest.hs

@@ -1,24 +1,10 @@
--- SPDX-FileCopyrightText: 2023 Google LLC
+-- SPDX-FileCopyrightText: 2023-2024 Google LLC
 --
 -- SPDX-License-Identifier: Apache-2.0
 
-import Clash.Prelude
-import Clash.Annotations.TH
+import Prelude
 
-import VexRiscv
-
-circuit ::
-  "CLK" ::: Clock System ->
-  "RST" ::: Reset System ->
-  "CPU_COMB_INPUT" ::: Signal System CpuIn ->
-  "JTAG_IN_" ::: Signal System JtagIn ->
-  "" :::
-    ( "CPU_OUTPUT" ::: Signal System CpuOut
-    , "JTAG_OUT_" ::: Signal System JtagOut)
-circuit clk rst input jtagIn =
-  vexRiscv clk rst input jtagIn
-
-makeTopEntity 'circuit
+import qualified Clash.Main as Clash
 
 main :: IO ()
-main = pure ()
+main = Clash.defaultMain ["Utils.Instance", "-main-is", "circuit", "--verilog"]

clash-vexriscv-sim/clash-vexriscv-sim.cabal

@@ -46,6 +46,13 @@ common common-options
 
     -- Prelude isn't imported by default as Clash offers Clash.Prelude
     NoImplicitPrelude
+
+  -- See https://github.com/clash-lang/clash-compiler/pull/2511
+  if impl(ghc >= 9.4)
+    CPP-Options: -DCLASH_OPAQUE=OPAQUE
+  else
+    CPP-Options: -DCLASH_OPAQUE=NOINLINE
+
   ghc-options:
     -Wall -Wcompat
 
@@ -76,6 +83,7 @@ library
   default-language: Haskell2010
   exposed-modules:
     Utils.Cpu
+    Utils.Instance
     Utils.Interconnect
     Utils.ProgramLoad
     Utils.ReadElf
@@ -88,19 +96,13 @@ library
     clash-vexriscv,
     elf >= 0.31 && < 0.32,
 
-executable clash
-  import: common-options
-  main-is: app/Clash.hs
-  build-Depends: base, clash-ghc
-
+-- XXX: Doesn't really belong in clash-vexriscv-SIM
 executable hdl-test
   import: common-options
   main-is: app/HdlTest.hs
   build-Depends:
     base,
-    clash-prelude,
-    clash-protocols,
-    clash-vexriscv,
+    clash-ghc,
     clash-vexriscv-sim,
 
 executable clash-vexriscv-bin

clash-vexriscv-sim/src/Utils/Instance.hs

@@ -0,0 +1,25 @@
+-- SPDX-FileCopyrightText: 2024 Google LLC
+--
+-- SPDX-License-Identifier: Apache-2.0
+{-# LANGUAGE CPP #-}
+
+-- | A dummy instance to test whether Clash can generate HDL for the VexRiscv
+module Utils.Instance where
+
+import Clash.Prelude
+import Clash.Annotations.TH
+
+import VexRiscv
+
+circuit ::
+  "CLK" ::: Clock System ->
+  "RST" ::: Reset System ->
+  "CPU_IN" ::: Signal System CpuIn ->
+  "JTAG_IN" ::: Signal System JtagIn ->
+  "" :::
+    ( "CPU_OUTPUT" ::: Signal System CpuOut
+    , "JTAG_OUT" ::: Signal System JtagOut )
+circuit clk rst input jtagIn =
+  vexRiscv clk rst input jtagIn
+{-# CLASH_OPAQUE circuit #-}
+makeTopEntity 'circuit

clash-vexriscv/clash-vexriscv.cabal

@@ -70,6 +70,13 @@ common common-options
 
     -- Prelude isn't imported by default as Clash offers Clash.Prelude
     NoImplicitPrelude
+
+  -- See https://github.com/clash-lang/clash-compiler/pull/2511
+  if impl(ghc >= 9.4)
+    CPP-Options: -DCLASH_OPAQUE=OPAQUE
+  else
+    CPP-Options: -DCLASH_OPAQUE=NOINLINE
+
   ghc-options:
     -Wall -Wcompat
 

clash-vexriscv/src/VexRiscv.hs

@@ -2,12 +2,12 @@
 --
 -- SPDX-License-Identifier: Apache-2.0
 
+{-# LANGUAGE CPP #-}
+{-# LANGUAGE MagicHash #-}
 {-# LANGUAGE NamedFieldPuns #-}
+{-# LANGUAGE QuasiQuotes #-}
 {-# LANGUAGE RecordWildCards #-}
-{-# LANGUAGE MagicHash #-}
 {-# LANGUAGE TemplateHaskellQuotes #-}
-{-# LANGUAGE QuasiQuotes #-}
--- {-# LANGUAGE AllowAmbiguousTypes #-}
 
 {-# OPTIONS_GHC -fconstraint-solver-iterations=10 #-}
 
@@ -356,7 +356,7 @@ vexRiscv# !_sourcePath clk rst0
       , FFI.jtag_debug_resetOut <$> output
       , FFI.jtag_TDO <$> output
       )
-{-# NOINLINE vexRiscv# #-}
+{-# CLASH_OPAQUE vexRiscv# #-}
 {-# ANN vexRiscv# (
     let
       primName = 'vexRiscv#