Fix VHDL and SystemVerilog gen for Xilinx oddr

Verilog correctly picked one of the possible arguments to inspect for
`ResetKind`, but the others picked the `KnownNat` constraint.

changelog/2024-10-26T14_40_52+02_00_fix_oddr

@@ -0,0 +1 @@
+FIXED: `oddr` in `Clash.Xilinx.DDR`: Fixed HDL generation erroring out for VHDL and SystemVerilog

clash-lib/prims/systemverilog/Clash_Xilinx_DDR.primitives.yaml

@@ -70,7 +70,7 @@
         ODDR #(
           .DDR_CLK_EDGE("SAME_EDGE"),
           .INIT(1'b0),
-          .SRTYPE(~IF ~ISSYNC[2] ~THEN "SYNC" ~ELSE "ASYNC" ~FI)
+          .SRTYPE(~IF ~ISSYNC[1] ~THEN "SYNC" ~ELSE "ASYNC" ~FI)
         ) ~GENSYM[~COMPNAME_ODDR][9] (
           .Q(~SYM[3][~SYM[8]]),
           .C(~ARG[3]),

clash-lib/prims/vhdl/Clash_Xilinx_DDR.primitives.yaml

@@ -79,13 +79,13 @@
         ~SYM[1] <= ~ARG[6];
         ~SYM[2] <= ~ARG[7];
 
-        ~GENSYM[gen_iddr][7] : for ~GENSYM[i][8] in ~SYM[3]'range generate
+        ~GENSYM[gen_oddr][7] : for ~GENSYM[i][8] in ~SYM[3]'range generate
         begin
           ~GENSYM[~COMPNAME_ODDR_inst][9] : ODDR
           generic map(
             DDR_CLK_EDGE => "SAME_EDGE",
             INIT => '0',
-            SRTYPE => ~IF ~ISSYNC[2] ~THEN "SYNC" ~ELSE "ASYNC" ~FI)
+            SRTYPE => ~IF ~ISSYNC[1] ~THEN "SYNC" ~ELSE "ASYNC" ~FI)
           port map (
             Q  => ~SYM[3](~SYM[8]),    -- 1-bit DDR output
             C  => ~ARG[3],   -- 1-bit clock input