extra whitespace in debug output

charlesreiss · Aug 23, 2021 · 239cfe1 · 239cfe1
1 parent 98fb48a
commit 239cfe1
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Showing 2 changed files with 2 additions and 1 deletion.
diff --git a/Cargo.toml b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "hclrs"
-version = "0.2.12"
+version = "0.2.13"
 authors = ["Charles Reiss <[email protected]>"]
 
 build = "build.rs" # LARLRPOP preprocessing

diff --git a/src/program.rs b/src/program.rs
@@ -1320,6 +1320,7 @@ impl RunningProgram {
                 _ => keys_normal.push(key.clone()),
             }
         }
+        writeln!(w, "")?;
         self.dump_wire_subtable(w, keys_builtin_input, "Values of inputs to built-in components:", false)?;
         self.dump_wire_subtable(w, keys_builtin_output, "Values of outputs of built-in components:", false)?;
         self.dump_wire_subtable(w, keys_register_bank, "Values of register bank signals:", false)?;