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[yxi] Rename calyx-axi-wrapper clock signal to ap_clk #2386

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@nathanielnrn nathanielnrn commented Jan 2, 2025

Another PR whittling down the changes present in #2267.
This PR changes the toplevel clock signal from clk to ap_clk. This should allow us to reuse the existing gen_xo.tcl and maintain backwards compatibility with the old verilog-axi-wrapper, without requiring a distinction between the two in the gen_xo.tcl file.

Also fixes a bsd vs gnu sed syntax error. The new command should work on both.
(bsd sed require terminating commands to end with a ;, gnu does not)

I'll also note that this PR touches a bunch of runt cocotb tests in tests/axi. I'm aware that there is a desire to get rid of large snapshots as they tend to get ignored. For now this setup is the best thing I have to make sure breaking changes aren't introduced to either axi-wrapper, so choosing to update them for now.

@nathanielnrn nathanielnrn changed the title [yxi] Rename [new] calyx-axi-wrapper clock signal to ap_clk [yxi] Rename calyx-axi-wrapper clock signal to ap_clk Jan 2, 2025
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