Feature: ESP32-C3 support

meson_options.txt

@@ -34,6 +34,7 @@ option(
 		'at32f4',
 		'ch579',
 		'efm',
+		'esp32',
 		'hc32',
 		'lpc',
 		'nrf',

src/Makefile

@@ -141,6 +141,7 @@ endif
 ifeq ($(ENABLE_RISCV), 1)
 CFLAGS += -DENABLE_RISCV=1
 SRC +=               \
+	esp32c3.c        \
 	riscv32.c        \
 	riscv64.c        \
 	riscv_debug.c    \

src/target/jep106.h

@@ -69,6 +69,7 @@
 #define JEP106_MANUFACTURER_RENESAS      0x423U /* Renesas */
 #define JEP106_MANUFACTURER_WCH          0x72aU /* "Nanjing Yihuo Technology", used by CH579 */
 #define JEP106_MANUFACTURER_XILINX       0x309U /* Xilinx - Technically 0x049, but they use Ikanos Communications' code */
+#define JEP106_MANUFACTURER_ESPRESSIF    0xc12U /* Espressif */
 /*
  * This JEP code should belong to "Andes Technology Corporation", but is used on RISC-V by GigaDevice,
  * so in the unlikely event we need to support chips by them, here be dragons.

src/target/jtag_devs.c

@@ -413,6 +413,19 @@ const jtag_dev_descr_s dev_descr[] = {
 #endif
 		.handler = riscv_jtag_dtm_handler,
 	},
+	{
+		.idcode = 0x00005c25U,
+		.idmask = 0x0fffffffU,
+#if ENABLE_DEBUG == 1
+		.descr = "RISC-V debug v0.13.",
+#endif
+		.handler = riscv_jtag_dtm_handler,
+		.ir_quirks =
+			{
+				.ir_length = 5,
+				.ir_value = 0x0005U,
+			},
+	},
 #endif
 #if defined(ENABLE_CORTEXAR) // && defined(ENABLE_SITARA)
 	{

src/target/meson.build

@@ -77,6 +77,7 @@ if is_firmware_build
 		'apollo3': 'Ambiq Apollo3 parts',
 		'ch579': 'CH579',
 		'efm': 'Energy Micro parts',
+		'esp32': 'Espressif parts',
 		'hc32': 'HC32 parts',
 		'lpc': 'LPC series parts',
 		'nrf': 'nRF series parts',
@@ -173,6 +174,11 @@ target_efm = declare_dependency(
 	dependencies: target_cortexm,
 )
 
+target_esp32 = declare_dependency(
+	sources: files('esp32c3.c'),
+	dependencies: target_riscv32,
+)
+
 target_hc32 = declare_dependency(
 	sources: files('hc32l110.c'),
 	dependencies: target_cortexm,
@@ -334,6 +340,7 @@ libbmd_target_deps = [
 	target_at32f4,
 	target_ch579,
 	target_efm,
+	target_esp32,
 	target_hc32,
 	target_lpc,
 	target_nrf,

src/target/riscv32.c

@@ -96,6 +96,9 @@ bool riscv32_probe(target_s *const target)
 	case JEP106_MANUFACTURER_RV_GIGADEVICE:
 		PROBE(gd32vf1_probe);
 		break;
+	case JEP106_MANUFACTURER_ESPRESSIF:
+		PROBE(esp32c3_probe);
+		break;
 	}
 
 #if PC_HOSTED == 0

src/target/riscv_debug.c

@@ -261,9 +261,6 @@ static void riscv_hart_memory_access_type(riscv_hart_s *hart);
 static const char *riscv_target_description(target_s *target);
 
 static bool riscv_check_error(target_s *target);
-static void riscv_halt_request(target_s *target);
-static void riscv_halt_resume(target_s *target, bool step);
-static target_halt_reason_e riscv_halt_poll(target_s *target, target_addr_t *watch);
 static void riscv_reset(target_s *target);
 
 void riscv_dmi_init(riscv_dmi_s *const dmi)
@@ -429,6 +426,12 @@ static bool riscv_hart_init(riscv_hart_s *const hart)
 	target->designer_code = hart->vendorid ? hart->vendorid : hart->dbg_module->dmi_bus->designer_code;
 	target->cpuid = hart->archid;
 
+	/*
+	 * Now we've identified the target, and before we can do things like trigger discovery
+	 * we need to first run any target-specific setup (eg, halting the WDTs on the ESP32-C3)
+	 * so the next steps won't get screwed up by them.
+	 */
+	esp32c3_target_prepare(target);
 	/* Now we're in a safe environment, leasurely read out the triggers, etc. */
 	riscv_hart_discover_triggers(hart);
 
@@ -851,7 +854,7 @@ static bool riscv_dm_poll_state(riscv_dm_s *const dbg_module, const uint32_t sta
 	return true;
 }
 
-static void riscv_halt_request(target_s *const target)
+void riscv_halt_request(target_s *const target)
 {
 	riscv_hart_s *const hart = riscv_hart_struct(target);
 	/* Request the hart to halt */
@@ -864,7 +867,7 @@ static void riscv_halt_request(target_s *const target)
 	(void)riscv_dm_write(hart->dbg_module, RV_DM_CONTROL, hart->hartsel);
 }
 
-static void riscv_halt_resume(target_s *target, const bool step)
+void riscv_halt_resume(target_s *const target, const bool step)
 {
 	riscv_hart_s *const hart = riscv_hart_struct(target);
 	/* Configure the debug controller for single-stepping as appropriate */
@@ -889,7 +892,7 @@ static void riscv_halt_resume(target_s *target, const bool step)
 	(void)riscv_dm_write(hart->dbg_module, RV_DM_CONTROL, hart->hartsel);
 }
 
-static target_halt_reason_e riscv_halt_poll(target_s *const target, target_addr_t *const watch)
+target_halt_reason_e riscv_halt_poll(target_s *const target, target_addr_t *const watch)
 {
 	(void)watch;
 	riscv_hart_s *const hart = riscv_hart_struct(target);

src/target/riscv_debug.h

@@ -252,6 +252,10 @@ uint8_t riscv_mem_access_width(const riscv_hart_s *hart, target_addr_t address,
 void riscv32_unpack_data(void *dest, uint32_t data, uint8_t access_width);
 uint32_t riscv32_pack_data(const void *src, uint8_t access_width);
 
+void riscv_halt_request(target_s *target);
+void riscv_halt_resume(target_s *target, bool step);
+target_halt_reason_e riscv_halt_poll(target_s *target, target_addr_t *watch);
+
 void riscv32_mem_read(target_s *target, void *dest, target_addr64_t src, size_t len);
 void riscv32_mem_write(target_s *target, target_addr64_t dest, const void *src, size_t len);
 

src/target/target_probe.c

@@ -150,7 +150,13 @@ TARGET_PROBE_WEAK_NOP(stm32mp15_ca7_probe)
 TARGET_PROBE_WEAK_NOP(stm32mp15_cm4_probe)
 TARGET_PROBE_WEAK_NOP(stm32wb0_probe)
 TARGET_PROBE_WEAK_NOP(zynq7_probe)
+TARGET_PROBE_WEAK_NOP(esp32c3_probe)
 
 LPC55_DP_PREPARE_WEAK_NOP(lpc55_dp_prepare)
+/*
+ * This isn't actually a probe routine, but it shares its signature with them,
+ * so uses the same no-op stub because we can get away with that.
+ */
+TARGET_PROBE_WEAK_NOP(esp32c3_target_prepare)
 
 #endif /* _WIN32 */

src/target/target_probe.h

@@ -101,7 +101,9 @@ bool stm32mp15_ca7_probe(target_s *target);
 bool stm32mp15_cm4_probe(target_s *target);
 bool stm32wb0_probe(target_s *target);
 bool zynq7_probe(target_s *target);
+bool esp32c3_probe(target_s *target);
 
 void lpc55_dp_prepare(adiv5_debug_port_s *dp);
+bool esp32c3_target_prepare(target_s *target);
 
 #endif /* TARGET_TARGET_PROBE_H */