RISCV: Add some quirks to be compatible with CH32V3x chips

src/Makefile

@@ -23,62 +23,66 @@ ifeq ($(ENABLE_DEBUG), 1)
 CFLAGS += -DENABLE_DEBUG
 endif
 
-SRC =              \
-	adiv5.c        \
-	adiv5_jtag.c   \
-	adiv5_swd.c    \
-	command.c      \
-	cortexa.c      \
-	cortexm.c      \
-	crc32.c        \
-	efm32.c        \
-	exception.c    \
-	gdb_if.c       \
-	gdb_main.c     \
-	gdb_hostio.c   \
-	gdb_packet.c   \
-	gdb_reg.c      \
-	hex_utils.c    \
-	hc32l110.c     \
-	imxrt.c        \
-	jtag_devs.c    \
-	jtag_scan.c    \
-	lmi.c          \
-	lpc_common.c   \
-	lpc11xx.c      \
-	lpc17xx.c      \
-	lpc15xx.c      \
-	lpc40xx.c      \
-	lpc43xx.c      \
-	lpc546xx.c     \
-	lpc55xx.c      \
-	kinetis.c      \
-	main.c         \
-	maths_utils.c  \
-	morse.c        \
-	msp432e4.c     \
-	msp432p4.c     \
-	nrf51.c        \
-	nxpke04.c      \
-	remote.c       \
-	rp.c           \
-	sam3x.c        \
-	sam4l.c        \
-	samd.c         \
-	samx5x.c       \
-	sfdp.c         \
-	spi.c          \
-	stm32f1.c      \
-	ch32f1.c       \
-	stm32f4.c      \
-	stm32h5.c      \
-	stm32h7.c      \
-	stm32l0.c      \
-	stm32l4.c      \
-	stm32g0.c      \
-	renesas.c      \
-	target.c       \
-	target_flash.c \
+SRC =                \
+	adiv5.c          \
+	adiv5_jtag.c     \
+	adiv5_swd.c      \
+	command.c        \
+	cortexa.c        \
+	cortexm.c        \
+	crc32.c          \
+	efm32.c          \
+	exception.c      \
+	gdb_if.c         \
+	gdb_main.c       \
+	gdb_hostio.c     \
+	gdb_packet.c     \
+	gdb_reg.c        \
+	hex_utils.c      \
+	hc32l110.c       \
+	imxrt.c          \
+	jtag_devs.c      \
+	jtag_scan.c      \
+	lmi.c            \
+	lpc_common.c     \
+	lpc11xx.c        \
+	lpc17xx.c        \
+	lpc15xx.c        \
+	lpc40xx.c        \
+	lpc43xx.c        \
+	lpc546xx.c       \
+	lpc55xx.c        \
+	kinetis.c        \
+	main.c           \
+	maths_utils.c    \
+	morse.c          \
+	msp432e4.c       \
+	msp432p4.c       \
+	nrf51.c          \
+	nxpke04.c        \
+	remote.c         \
+	riscv32.c        \
+	riscv64.c        \
+	riscv_debug.c    \
+	riscv_jtag_dtm.c \
+	rp.c             \
+	sam3x.c          \
+	sam4l.c          \
+	samd.c           \
+	samx5x.c         \
+	sfdp.c           \
+	spi.c            \
+	stm32f1.c        \
+	ch32f1.c         \
+	stm32f4.c        \
+	stm32h5.c        \
+	stm32h7.c        \
+	stm32l0.c        \
+	stm32l4.c        \
+	stm32g0.c        \
+	renesas.c        \
+	target.c         \
+	target_flash.c   \
 	target_probe.c
 
 ifeq (,$(filter all_platforms,$(MAKECMDGOALS)))

src/gdb_main.c

@@ -682,10 +682,13 @@ static void handle_z_packet(char *packet, const size_t plen)
 	else
 		ret = target_breakwatch_clear(cur_target, type, addr, len);
 
+	/* If the target handler was unable to set/clear the break/watch-point, return an error */
 	if (ret < 0)
 		gdb_putpacketz("E01");
+	/* If the handler does not support the kind requested, return empty string */
 	else if (ret > 0)
 		gdb_putpacketz("");
+	/* Otherwise let GDB know that everything went well */
 	else
 		gdb_putpacketz("OK");
 }

src/target/adiv5.h

@@ -185,6 +185,11 @@
 #define JTAG_IDCODE_PARTNO_MASK     (0xffffU << JTAG_IDCODE_PARTNO_OFFSET)
 #define JTAG_IDCODE_DESIGNER_OFFSET 1U
 #define JTAG_IDCODE_DESIGNER_MASK   (0x7ffU << JTAG_IDCODE_DESIGNER_OFFSET)
+/* Bits 10:7 - JEP-106 Continuation code */
+/* Bits 6:0 - JEP-106 Identity code */
+#define JTAG_IDCODE_DESIGNER_JEP106_CONT_OFFSET 7U
+#define JTAG_IDCODE_DESIGNER_JEP106_CONT_MASK   (0xfU << ADIV5_DP_DESIGNER_JEP106_CONT_OFFSET)
+#define JTAG_IDCODE_DESIGNER_JEP106_CODE_MASK   (0x7fU)
 
 #define JTAG_IDCODE_ARM_DPv0 UINT32_C(0x4ba00477)
 

src/target/jep106.h

@@ -68,6 +68,11 @@
 #define JEP106_MANUFACTURER_RASPBERRY    0x913U /* Raspberry Pi */
 #define JEP106_MANUFACTURER_RENESAS      0x423U /* Renesas */
 #define JEP106_MANUFACTURER_XILINX       0x309U /* Xilinx */
+/*
+ * This JEP code should belong to "Andes Technology Corporation", but is used on RISC-V by GigaDevice,
+ * so in the unlikely event we need to support chips by them, here be dragons.
+ */
+#define JEP106_MANUFACTURER_RV_GIGADEVICE 0x61eU
 
 /*
  * This code is not listed in the JEP106 standard, but is used by some stm32f1 clones

src/target/jtag_devs.c

@@ -22,6 +22,7 @@
 #include "general.h"
 #include "jtag_scan.h"
 #include "adiv5.h"
+#include "riscv_debug.h"
 #include "jtag_devs.h"
 
 const jtag_dev_descr_s dev_descr[] = {
@@ -112,9 +113,10 @@ const jtag_dev_descr_s dev_descr[] = {
 			},
 	},
 	{
-		.idcode = 0x0000063dU,
-		.idmask = 0x00000fffU,
-		.descr = "Xambala: RVDBG013.",
+		.idcode = 0x0000563dU,
+		.idmask = 0x0fffffffU,
+		.descr = "RISC-V debug v0.13.",
+		.handler = riscv_jtag_dtm_handler,
 	},
 	{
 		.idcode = 0x000007a3U,