stm32f1: flash_write: (fixup) Use 32-bit writes on AT32F40/41 and GD32

* Rename the TOPT flag to be more generic * Set it in Arterytek detect code on success
blackmagic-debug · Jan 8, 2024 · f10b17c · f10b17c
1 parent 829bf1f
commit f10b17c
Showing 1 changed file with 6 additions and 4 deletions.
diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c
@@ -109,7 +109,7 @@ static bool stm32f1_mass_erase(target_s *target);
 #define DBGMCU_IDCODE_MM32L0 0x40013400U
 #define DBGMCU_IDCODE_MM32F3 0x40007080U
 
-#define STM32F1_TOPT_GIGADEVICE (1U << 8U)
+#define STM32F1_TOPT_32BIT_WRITES (1U << 8U)
 
 static void stm32f1_add_flash(target_s *target, uint32_t addr, size_t length, size_t erasesize)
 {
@@ -191,7 +191,7 @@ bool gd32f1_probe(target_s *target)
 		stm32f1_add_flash(target, 0x8000000, (size_t)flash_size * 1024U, block_size);
 
 	target->part_id = device_id;
-	target->target_options |= STM32F1_TOPT_GIGADEVICE;
+	target->target_options |= STM32F1_TOPT_32BIT_WRITES;
 	target->mass_erase = stm32f1_mass_erase;
 	target_add_ram(target, 0x20000000, ram_size * 1024U);
 	target_add_commands(target, stm32f1_cmd_list, target->driver);
@@ -283,6 +283,7 @@ static bool at32f40_detect(target_s *target, const uint16_t part_id)
 	target_add_ram(target, 0x20000000, 96U * 1024U);
 	target->driver = "AT32F403A/407";
 	target->part_id = part_id;
+	target->target_options |= STM32F1_TOPT_32BIT_WRITES;
 	target->mass_erase = stm32f1_mass_erase;
 	return true;
 }
@@ -320,6 +321,7 @@ static bool at32f41_detect(target_s *target, const uint16_t part_id)
 	target_add_ram(target, 0x20000000, 32U * 1024U);
 	target->driver = "AT32F415";
 	target->part_id = part_id;
+	target->target_options |= STM32F1_TOPT_32BIT_WRITES;
 	target->mass_erase = stm32f1_mass_erase;
 	return true;
 }
@@ -685,8 +687,8 @@ static bool stm32f1_flash_write(target_flash_s *flash, target_addr_t dest, const
 	const size_t offset = stm32f1_bank1_length(dest, len);
 	DEBUG_TARGET("%s: at %08" PRIx32 " for %zu bytes\n", __func__, dest, len);
 
-	/* Allow wider writes on Gigadevices (is there a better way to hook this?) */
-	const align_e psize = (target->target_options & STM32F1_TOPT_GIGADEVICE) ? ALIGN_32BIT : ALIGN_16BIT;
+	/* Allow wider writes on Gigadevices and Arterytek */
+	const align_e psize = (target->target_options & STM32F1_TOPT_32BIT_WRITES) ? ALIGN_32BIT : ALIGN_16BIT;
 
 	/* Start by writing any bank 1 data */
 	if (offset) {