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stm32f1: flash_write: Use 32-bit accesses on all GD32 targets
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* All of currently supported GD32 families support 16-bit/32-bit flash writes
* Enable them for a significant reprogramming performance boost (~+50%)
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ALTracer committed Jan 4, 2024
1 parent e7ab3fa commit c54facc
Showing 1 changed file with 5 additions and 2 deletions.
7 changes: 5 additions & 2 deletions src/target/stm32f1.c
Original file line number Diff line number Diff line change
Expand Up @@ -682,6 +682,9 @@ static bool stm32f1_flash_write(target_flash_s *flash, target_addr_t dest, const
const size_t offset = stm32f1_bank1_length(dest, len);
DEBUG_TARGET("%s: at %08" PRIx32 " for %zu bytes\n", __func__, dest, len);

/* Allow wider writes on Gigadevices (is there a better way to hook this?) */
const align_e psize = (!strncmp(target->driver, "GD32", 4)) ? ALIGN_32BIT : ALIGN_16BIT;

/* Start by writing any bank 1 data */
if (offset) {
stm32f1_flash_clear_eop(target, FLASH_BANK1_OFFSET);
Expand All @@ -691,7 +694,7 @@ static bool stm32f1_flash_write(target_flash_s *flash, target_addr_t dest, const
if (target->designer_code == JEP106_MANUFACTURER_RV_GIGADEVICE && target->cpuid == 0x80000022U)
target_mem_write(target, dest, src, offset);
else
cortexm_mem_write_sized(target, dest, src, offset, ALIGN_16BIT);
cortexm_mem_write_sized(target, dest, src, offset, psize);

/* Wait for completion or an error */
if (!stm32f1_flash_busy_wait(target, FLASH_BANK1_OFFSET, NULL))
Expand All @@ -709,7 +712,7 @@ static bool stm32f1_flash_write(target_flash_s *flash, target_addr_t dest, const
if (target->designer_code == JEP106_MANUFACTURER_RV_GIGADEVICE && target->cpuid == 0x80000022U)
target_mem_write(target, dest + offset, data + offset, remainder);
else
cortexm_mem_write_sized(target, dest + offset, data + offset, remainder, ALIGN_16BIT);
cortexm_mem_write_sized(target, dest + offset, data + offset, remainder, psize);

/* Wait for completion or an error */
if (!stm32f1_flash_busy_wait(target, FLASH_BANK2_OFFSET, NULL))
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