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target: Support 64-bit address for break/watch point
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This change breakwatch::addr to be 64-bit as this will be required for
ARMv8 AArch64 support.

This also change the layout of breakwatch to avoid extraneous padding in
64-bit and reduce the size of the reserved array to 64 bits.

Signed-off-by: Mary Guillemard <[email protected]>
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@marysaka
marysaka committed Dec 15, 2024
1 parent 90d23db commit 9086642
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Showing 8 changed files with 16 additions and 16 deletions.
5 changes: 3 additions & 2 deletions src/gdb_main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -928,7 +928,7 @@ void gdb_poll_target(void)
}

/* poll target */
target_addr_t watch;
target_addr64_t watch;
target_halt_reason_e reason = target_halt_poll(cur_target, &watch);
if (!reason)
return;
Expand All @@ -947,7 +947,8 @@ void gdb_poll_target(void)
gdb_putpacket_str_f("T%02Xthread:1;", GDB_SIGINT);
break;
case TARGET_HALT_WATCHPOINT:
gdb_putpacket_str_f("T%02Xwatch:%08" PRIX32 ";", GDB_SIGTRAP, watch);
gdb_putpacket_str_f(
"T%02Xwatch:%0" PRIX32 "%08" PRIX32 ";", GDB_SIGTRAP, (uint32_t)(watch >> 32U), (uint32_t)watch);
break;
case TARGET_HALT_FAULT:
gdb_putpacket_str_f("T%02Xthread:1;", GDB_SIGSEGV);
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2 changes: 1 addition & 1 deletion src/include/target.h
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Expand Up @@ -98,7 +98,7 @@ typedef enum target_halt_reason {

void target_reset(target_s *target);
void target_halt_request(target_s *target);
target_halt_reason_e target_halt_poll(target_s *target, target_addr_t *watch);
target_halt_reason_e target_halt_poll(target_s *target, target_addr64_t *watch);
void target_halt_resume(target_s *target, bool step);
void target_set_cmdline(target_s *target, const char *cmdline, size_t cmdline_len);
void target_set_heapinfo(target_s *target, target_addr_t heap_base, target_addr_t heap_limit, target_addr_t stack_base,
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2 changes: 1 addition & 1 deletion src/rtt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -394,7 +394,7 @@ void poll_rtt(target_s *const cur_target)
rtt_halt = target_mem_access_needs_halt(cur_target);

bool resume_target = false;
target_addr_t watch;
target_addr64_t watch;
if (rtt_halt && target_halt_poll(cur_target, &watch) == TARGET_HALT_RUNNING) {
/* briefly halt target during target memory access */
target_halt_request(cur_target);
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4 changes: 2 additions & 2 deletions src/target/cortexar.c
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Original file line number Diff line number Diff line change
Expand Up @@ -393,7 +393,7 @@ static size_t cortexar_reg_read(target_s *target, uint32_t reg, void *data, size
static size_t cortexar_reg_write(target_s *target, uint32_t reg, const void *data, size_t max);

static void cortexar_reset(target_s *target);
static target_halt_reason_e cortexar_halt_poll(target_s *target, target_addr_t *watch);
static target_halt_reason_e cortexar_halt_poll(target_s *target, target_addr64_t *watch);
static void cortexar_halt_request(target_s *target);
static void cortexar_halt_resume(target_s *target, bool step);
static bool cortexar_halt_and_wait(target_s *target);
Expand Down Expand Up @@ -1405,7 +1405,7 @@ static void cortexar_halt_request(target_s *const target)
}
}

static target_halt_reason_e cortexar_halt_poll(target_s *const target, target_addr_t *const watch)
static target_halt_reason_e cortexar_halt_poll(target_s *const target, target_addr64_t *const watch)
{
volatile uint32_t dscr = 0;
TRY (EXCEPTION_ALL) {
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4 changes: 2 additions & 2 deletions src/target/cortexm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ static size_t cortexm_reg_read(target_s *target, uint32_t reg, void *data, size_
static size_t cortexm_reg_write(target_s *target, uint32_t reg, const void *data, size_t max);

static void cortexm_reset(target_s *target);
static target_halt_reason_e cortexm_halt_poll(target_s *target, target_addr_t *watch);
static target_halt_reason_e cortexm_halt_poll(target_s *target, target_addr64_t *watch);
static void cortexm_halt_request(target_s *target);
static int cortexm_fault_unwind(target_s *target);

Expand Down Expand Up @@ -828,7 +828,7 @@ static void cortexm_halt_request(target_s *target)
}
}

static target_halt_reason_e cortexm_halt_poll(target_s *target, target_addr_t *watch)
static target_halt_reason_e cortexm_halt_poll(target_s *target, target_addr64_t *watch)
{
cortexm_priv_s *priv = target->priv;

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4 changes: 2 additions & 2 deletions src/target/riscv_debug.c
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Expand Up @@ -286,7 +286,7 @@ static const char *riscv_target_description(target_s *target);
static bool riscv_check_error(target_s *target);
static void riscv_halt_request(target_s *target);
static void riscv_halt_resume(target_s *target, bool step);
static target_halt_reason_e riscv_halt_poll(target_s *target, target_addr_t *watch);
static target_halt_reason_e riscv_halt_poll(target_s *target, target_addr64_t *watch);
static void riscv_reset(target_s *target);

void riscv_dmi_init(riscv_dmi_s *const dmi)
Expand Down Expand Up @@ -1033,7 +1033,7 @@ static void riscv_halt_resume(target_s *target, const bool step)
(void)riscv_dm_write(hart->dbg_module, RV_DM_CONTROL, hart->hartsel);
}

static target_halt_reason_e riscv_halt_poll(target_s *const target, target_addr_t *const watch)
static target_halt_reason_e riscv_halt_poll(target_s *const target, target_addr64_t *const watch)
{
(void)watch;
riscv_hart_s *const hart = riscv_hart_struct(target);
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2 changes: 1 addition & 1 deletion src/target/target.c
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Original file line number Diff line number Diff line change
Expand Up @@ -424,7 +424,7 @@ static const char *target_halt_reason_str(const target_halt_reason_e reason)
}
#endif

target_halt_reason_e target_halt_poll(target_s *target, target_addr_t *watch)
target_halt_reason_e target_halt_poll(target_s *target, target_addr64_t *watch)
{
if (target->halt_poll) {
const target_halt_reason_e reason = target->halt_poll(target, watch);
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9 changes: 4 additions & 5 deletions src/target/target_internal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -103,12 +103,11 @@ struct target_command {
typedef struct breakwatch breakwatch_s;

struct breakwatch {
/* XXX: This needs adjusting for 64-bit operations */
breakwatch_s *next;
target_breakwatch_e type;
target_addr32_t addr;
target_addr64_t addr;
size_t size;
uint32_t reserved[4]; /* For use by the implementing driver */
target_breakwatch_e type;
uint32_t reserved[2]; /* For use by the implementing driver */
};

#define MAX_CMDLINE 81
Expand Down Expand Up @@ -137,7 +136,7 @@ struct target {
void (*reset)(target_s *target);
void (*extended_reset)(target_s *target);
void (*halt_request)(target_s *target);
target_halt_reason_e (*halt_poll)(target_s *target, target_addr_t *watch);
target_halt_reason_e (*halt_poll)(target_s *target, target_addr64_t *watch);
void (*halt_resume)(target_s *target, bool step);

/* Break-/watchpoint functions */
Expand Down

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