misc: Fix typos

Signed-off-by: Francois Berder <[email protected]>

src/gdb_main.c

@@ -525,7 +525,7 @@ static void exec_q_thread_info(const char *packet, const size_t length)
 /*
  * GDB will send the packet 'QStartNoAckMode' to enable NoAckMode
  *
- * To tell GDB to not use NoAckMode do the following before connnecting to the probe:
+ * To tell GDB to not use NoAckMode do the following before connecting to the probe:
  * set remote noack-packet off
  */
 static void exec_q_noackmode(const char *packet, const size_t length)

src/gdb_packet.c

@@ -47,7 +47,7 @@ void gdb_set_noackmode(bool enable)
 	/*
 	 * If we were asked to disable NoAckMode, and it was previously enabled,
 	 * it might mean we got a packet we determined to be the first of a new
-	 * GDB session, and as such it was not acknoledged (before GDB enabled NoAckMode),
+	 * GDB session, and as such it was not acknowledged (before GDB enabled NoAckMode),
 	 * better late than never.
 	 *
 	 * If we were asked after the connection was terminated, sending the ack will have no effect.

src/platforms/common/blackpill-f4/README.md

@@ -74,7 +74,7 @@ For other firmware upgrade instructions see the [Firmware Upgrade](https://black
 
 ## SWD/JTAG frequency setting
 
-In special cases the SWD/JTAG frequency needs to be adapted. The fequency can be set to `900k`, as this value was found to be helpful in practice, using:
+In special cases the SWD/JTAG frequency needs to be adapted. The frequency can be set to `900k`, as this value was found to be helpful in practice, using:
 
 ```
 mon freq 900k

src/platforms/common/usb_serial.c

@@ -447,7 +447,7 @@ void debug_monitor_handler(void)
 	__asm__("bx lr");
 }
 #else
-/* This defines stubs for the newlib fake file IO layer for compatability with GCC 12 `-spec=nosys.spec` */
+/* This defines stubs for the newlib fake file IO layer for compatibility with GCC 12 `-spec=nosys.spec` */
 
 /* NOLINTNEXTLINE(bugprone-reserved-identifier,cert-dcl37-c,cert-dcl51-cpp) */
 int _write(const int file, const void *const buffer, const size_t length)

src/platforms/hosted/bmp_libusb.c

@@ -524,7 +524,7 @@ int find_debuggers(bmda_cli_options_s *cl_opts, bmda_probe_s *info)
 	/* Count up how many were found and filter the list for a match to the program options request */
 	const size_t probes = probe_info_count(probe_list);
 	const probe_info_s *probe = NULL;
-	/* If there's just one probe and we didn't get match critera, pick it */
+	/* If there's just one probe and we didn't get match criteria, pick it */
 	if (probes == 1 && !cl_opts->opt_serial && !cl_opts->opt_position)
 		probe = probe_list;
 	else /* Otherwise filter the list */
@@ -569,7 +569,7 @@ int find_debuggers(bmda_cli_options_s *cl_opts, bmda_probe_s *info)
  *
  * NB: The lengths represent the maximum number of expected bytes and the actual amount
  *   sent/received may be less (per libusb's documentation). If used, rx_buffer must be
- *   suitably intialised up front to avoid UB reads when accessed.
+ *   suitably initialised up front to avoid UB reads when accessed.
  */
 int bmda_usb_transfer(
 	usb_link_s *link, const void *tx_buffer, size_t tx_len, void *rx_buffer, size_t rx_len, uint16_t timeout)

src/platforms/hosted/bmp_remote.c

@@ -86,7 +86,7 @@ bool remote_init(const bool power_up)
 		const uint64_t version = remote_decode_response(buffer + 1, length - 1);
 		switch (version) {
 		case 0:
-			/* protocol version number 0 coresponds to an enhanced v0 protocol probe ("v0+") */
+			/* protocol version number 0 corresponds to an enhanced v0 protocol probe ("v0+") */
 			remote_v0_plus_init();
 			break;
 		case 1:

src/platforms/hosted/bmp_serial.c

@@ -335,7 +335,7 @@ int find_debuggers(bmda_cli_options_s *cl_opts, bmda_probe_s *info)
 	/* Count up how many were found and filter the list for a match to the program options request */
 	const size_t probes = probe_info_count(probe_list);
 	const probe_info_s *probe = NULL;
-	/* If there's just one probe and we didn't get match critera, pick it */
+	/* If there's just one probe and we didn't get match criteria, pick it */
 	if (probes == 1U && !cl_opts->opt_serial && !cl_opts->opt_position)
 		probe = probe_list;
 	else /* Otherwise filter the list */

src/platforms/hosted/cmsis_dap.c

@@ -318,7 +318,7 @@ dap_version_s dap_adaptor_version(const dap_info_e version_kind)
 	if ((size_t)(end - version_str) >= version_length || end[0] != '.')
 		return version;
 
-	/* Now skip the delimeter and try to parse out the next component */
+	/* Now skip the delimiter and try to parse out the next component */
 	begin = end + 1U;
 	const uint16_t minor = strtoul(begin, &end, 10);
 	/* If that failed, return just the major */
@@ -329,7 +329,7 @@ dap_version_s dap_adaptor_version(const dap_info_e version_kind)
 	if ((size_t)(end - version_str) >= version_length || end[0] != '.')
 		return version;
 
-	/* Finally skip the delimeter and try to parse out the final component */
+	/* Finally skip the delimiter and try to parse out the final component */
 	begin = end + 1U;
 	const uint16_t revision = strtoul(begin, &end, 10);
 	/* If that failed, return just the major + minor */

src/platforms/hosted/ftdi_bmp.c

@@ -774,7 +774,7 @@ void ftdi_jtag_tdi_tdo_seq(uint8_t *data_out, const bool final_tms, const uint8_
 		ftdi_mpsse_cmd_bits_s command = {
 			MPSSE_WRITE_TMS | (data_out ? MPSSE_DO_READ : 0) | MPSSE_LSB | MPSSE_BITMODE | MPSSE_WRITE_NEG};
 		ftdi_buffer_write_val(command);
-		/* The LSb determins what TMS gets set to */
+		/* The LSb determines what TMS gets set to */
 		uint8_t data = 1U;
 		/* If there's data to send, queue it */
 		if (data_in) {
@@ -798,7 +798,7 @@ void ftdi_jtag_tdi_tdo_seq(uint8_t *data_out, const bool final_tms, const uint8_
 			const size_t shift = bits - (final_tms ? 1U : 0U);
 			data_out[bytes] >>= 8U - shift;
 		}
-		/* And read the data assocated with the TMS transaction and adjust the final byte */
+		/* And read the data associated with the TMS transaction and adjust the final byte */
 		if (final_tms) {
 			uint8_t value = 0;
 			ftdi_buffer_read_val(value);

src/platforms/hosted/jlink.c

@@ -419,7 +419,7 @@ static bool jlink_get_interfaces(void)
 		jlink.available_interfaces = read_le4(buffer, 0);
 	}
 
-	/* Print the available interfaces, marking the selected one, and unsuported ones */
+	/* Print the available interfaces, marking the selected one, and unsupported ones */
 	const uint8_t selected_interface = jlink_selected_interface();
 	DEBUG_INFO("Available interfaces: \n");
 	for (size_t i = 0; i < JLINK_INTERFACE_MAX; i++) {

src/platforms/hosted/jlink_swd.c

@@ -210,7 +210,7 @@ static uint32_t jlink_adiv5_raw_read_no_check(const uint16_t addr)
 		DEBUG_ERROR("jlink_adiv5_raw_read_no_check failed\n");
 		return 0U;
 	}
-	/* Extract the data phase and return it if the transaction suceeded */
+	/* Extract the data phase and return it if the transaction succeeded */
 	const uint32_t data = read_le4(response, 0);
 	DEBUG_PROBE("jlink_adiv5_raw_read_no_check %04x -> %08" PRIx32 " %s\n", addr, data,
 		__builtin_parity(data) ^ response[4] ? "ERR" : "OK");

src/platforms/hosted/remote/protocol_v0_adiv5.c

@@ -55,7 +55,7 @@ static bool remote_adiv5_check_error(const char *const func, const char *const b
 	/* Check if the firmware is reporting some other kind of error */
 	else if (buffer[0] != REMOTE_RESP_OK)
 		DEBUG_ERROR("%s: Firmware reported unexpected error: %c\n", func, buffer[0]);
-	/* Return whether the remote indicated the request was successfull */
+	/* Return whether the remote indicated the request was successful */
 	return buffer[0] == REMOTE_RESP_OK;
 }
 

src/platforms/hosted/remote/protocol_v1_adiv5.c

@@ -55,7 +55,7 @@ static bool remote_adiv5_check_error(const char *const func, const char *const b
 	/* Check if the firmware is reporting some other kind of error */
 	else if (buffer[0] != REMOTE_RESP_OK)
 		DEBUG_ERROR("%s: Firmware reported unexpected error: %c\n", func, buffer[0]);
-	/* Return whether the remote indicated the request was successfull */
+	/* Return whether the remote indicated the request was successful */
 	return buffer[0] == REMOTE_RESP_OK;
 }
 

src/platforms/hosted/remote/protocol_v3_adiv5.c

@@ -53,7 +53,7 @@ static bool remote_adiv5_check_error(
 		/* If the error part of the response code indicates a fault, store the fault value */
 		if (error == REMOTE_ERROR_FAULT)
 			dp->fault = response_code >> 8U;
-		/* If the error part indicates an exception had occured, make that happen here too */
+		/* If the error part indicates an exception had occurred, make that happen here too */
 		else if (error == REMOTE_ERROR_EXCEPTION)
 			raise_exception(response_code >> 8U, "Remote protocol exception");
 		/* Otherwise it's an unexpected error */
@@ -65,7 +65,7 @@ static bool remote_adiv5_check_error(
 	/* Check if the firmware is reporting some other kind of error */
 	else if (buffer[0] != REMOTE_RESP_OK)
 		DEBUG_ERROR("%s: Firmware reported unexpected error: %c\n", func, buffer[0]);
-	/* Return whether the remote indicated the request was successfull */
+	/* Return whether the remote indicated the request was successful */
 	return buffer[0] == REMOTE_RESP_OK;
 }
 

src/platforms/hosted/stlinkv2.c

@@ -849,7 +849,7 @@ static void stlink_v2_set_frequency(const uint32_t freq)
 		stlink_v2_divisor = 1U << ulog2(divisor);
 		stlink_v2_divisor /= STLINK_V2_JTAG_MUL_FACTOR;
 	} else {
-		/* Adjust the clock frequency request to result in the corrector dividor */
+		/* Adjust the clock frequency request to result in the corrector divider */
 		const uint32_t adjusted_freq = MAX(STLINK_V2_MIN_SWD_CLOCK_FREQ, MIN(freq, STLINK_V2_MAX_SWD_CLOCK_FREQ) + 1U);
 		const uint32_t divisor = STLINK_V2_CPU_CLOCK_FREQ / adjusted_freq;
 		/* Then compute the divisor using the multiplication factor */

src/platforms/native/platform.c

@@ -221,7 +221,7 @@ void platform_init(void)
 		 * Configure Timer 1 to run the the power control pin PWM and switch the timer on
 		 * NB: We don't configure the pin mode here but rather we configure it to the alt-mode and back in
 		 * platform_target_set_power() below due to GD32 errata involving PB2 (AUX serial LED).
-		 * See §3.7.6 of the GD32F103 Compatability Summary for details.
+		 * See §3.7.6 of the GD32F103 Compatibility Summary for details.
 		 */
 		timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
 		/* Use PWM mode 1 so that the signal generated is low till it exceeds the set value */

src/remote.c

@@ -488,7 +488,7 @@ static void remote_packet_process_adiv5(const char *const packet, const size_t p
 static void remote_spi_respond(const bool result)
 {
 	if (result)
-		/* If the request suceeded, send an OK response */
+		/* If the request succeeded, send an OK response */
 		remote_respond(REMOTE_RESP_OK, 0);
 	else
 		/* Otherwise signal that something went wrong with the request */

src/target/adiv5.c

@@ -810,7 +810,7 @@ uint32_t adiv5_dp_read_dpidr(adiv5_debug_port_s *const dp)
 void adiv5_dp_init(adiv5_debug_port_s *const dp)
 {
 	/*
-	 * We have to initialse the DP routines up front before any adiv5_* functions are called or
+	 * We have to initialise the DP routines up front before any adiv5_* functions are called or
 	 * bad things happen under BMDA (particularly CMSIS-DAP)
 	 */
 	dp->ap_write = firmware_ap_write;
@@ -912,7 +912,7 @@ void adiv5_dp_init(adiv5_debug_port_s *const dp)
 	platform_timeout_s timeout;
 	platform_timeout_set(&timeout, 250);
 
-	/* Start by resetting the DP contol state so the debug domain powers down */
+	/* Start by resetting the DP control state so the debug domain powers down */
 	adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, 0U);
 	uint32_t status = ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK;
 	/* Wait for the acknowledgements to go low */

src/target/adiv5.h

@@ -157,7 +157,7 @@
 #define ADIV5_AP_CSW_HPROT1           (1U << 25U)
 #define ADIV5_AP_CSW_SPIDEN           (1U << 23U)
 /* Bits 22:16 - Reserved */
-/* Bit 15 - MTE (Memory Tagging Enable) for AXI busses */
+/* Bit 15 - MTE (Memory Tagging Enable) for AXI buses */
 #define ADIV5_AP_CSW_MTE (1U << 15U)
 /* Bits 14:12 - Reserved */
 /* Bits 11:8 - Mode, must be zero */

src/target/adiv5_jtag.c

@@ -59,7 +59,7 @@ void adiv5_jtag_dp_handler(const uint8_t dev_index)
 	const uint32_t idcode = jtag_devs[dev_index].jd_idcode;
 	/*
 	 * Pulling out the designer code which will be used to attempt to detect a DPv0 DP.
-	 * This will get overriden later by DPIDR if the DP turns out to be DPv1+.
+	 * This will get overridden later by DPIDR if the DP turns out to be DPv1+.
 	 */
 	const uint16_t designer = (idcode & JTAG_IDCODE_DESIGNER_MASK) >> JTAG_IDCODE_DESIGNER_OFFSET;
 	/*

src/target/cortexar.c

@@ -225,7 +225,7 @@ static const uint16_t cortexar_spsr_encodings[5] = {
  */
 #define ENCODE_CP_ACCESS(coproc, opc1, rt, crn, crm, opc2) \
 	(((opc1) << 21U) | ((crn) << 16U) | ((rt) << 12U) | ((coproc) << 8U) | ((opc2) << 5U) | (crm))
-/* Packs a CRn and CRm value for the coprocessor IO rouines below to unpack */
+/* Packs a CRn and CRm value for the coprocessor IO routines below to unpack */
 #define ENCODE_CP_REG(n, m, opc1, opc2) \
 	((((n)&0xfU) << 4U) | ((m)&0xfU) | (((opc1)&0x7U) << 8U) | (((opc2)&0x7U) << 12U))
 
@@ -332,7 +332,7 @@ static const gdb_reg_type_e cortexr_spr_types[] = {
 
 /* clang-format off */
 static_assert(ARRAY_LENGTH(cortexr_spr_types) == ARRAY_LENGTH(cortexr_spr_names),
-	"SPR array length mistmatch! SPR type array should ahve the same length as SPR name array."
+	"SPR array length mistmatch! SPR type array should have the same length as SPR name array."
 );
 /* clang-format on */
 
@@ -586,7 +586,7 @@ static target_addr_t cortexar_virt_to_phys(target_s *const target, const target_
 		return virt_addr;
 
 	/*
-	 * Now we know the target is VMSA and so has the address translation machinary,
+	 * Now we know the target is VMSA and so has the address translation machinery,
 	 * start by loading r0 with the VA to translate and request its translation
 	 */
 	cortexar_core_reg_write(target, 0U, virt_addr);
@@ -998,7 +998,7 @@ static void cortexar_mem_read(target_s *const target, void *const dest, const ta
 		cortexr_mem_read_fast(target, (uint32_t *)dest, len >> 2U);
 	else
 		cortexr_mem_read_slow(target, (uint8_t *)dest, src, len);
-	/* Deal with any data faults that occured */
+	/* Deal with any data faults that occurred */
 	cortexr_mem_handle_fault(target, __func__, fault_status, fault_addr);
 }
 
@@ -1076,7 +1076,7 @@ static void cortexar_mem_write(
 		cortexr_mem_write_fast(target, (const uint32_t *)src, len >> 2U);
 	else
 		cortexr_mem_write_slow(target, dest, (const uint8_t *)src, len);
-	/* Deal with any data faults that occured */
+	/* Deal with any data faults that occurred */
 	cortexr_mem_handle_fault(target, __func__, fault_status, fault_addr);
 }
 
@@ -1153,7 +1153,7 @@ static ssize_t cortexar_reg_read(target_s *const target, const uint32_t reg, voi
 
 static ssize_t cortexar_reg_write(target_s *const target, const uint32_t reg, const void *const data, const size_t max)
 {
-	/* Try to get a poitner to the storage for the requested register, and return -1 if that fails */
+	/* Try to get a pointer to the storage for the requested register, and return -1 if that fails */
 	void *const reg_ptr = cortexar_reg_ptr(target, reg);
 	if (!reg_ptr)
 		return -1;
@@ -1289,7 +1289,7 @@ static void cortexar_halt_resume(target_s *const target, const bool step)
 
 	uint32_t dscr = cortex_dbg_read32(target, CORTEXAR_DBG_DSCR);
 	/*
-	 * If we're setting up to single-step the core, configure the final breakpoint slot approrpriately.
+	 * If we're setting up to single-step the core, configure the final breakpoint slot appropriately.
 	 * We always keep the final supported breakpoint reserved for this purpose so
 	 * `priv->base.breakpoints_available` represents this slot index.
 	 * Additionally, adjust DSCR to disable interrupts as necessary.
@@ -1505,9 +1505,9 @@ static size_t cortexar_build_target_fpu_description(char *const buffer, size_t m
  * This function creates the target description XML string for a Cortex-A/R part.
  * This is done this way to decrease string duplications and thus code size,
  * making it unfortunately much less readable than the string literal it is
- * equivilent to.
+ * equivalent to.
  *
- * The string it creates is aproximately the following:
+ * The string it creates is approximately the following:
  * <?xml version="1.0"?>
  * <!DOCTYPE target SYSTEM "gdb-target.dtd">
  * <target>

src/target/imxrt.c

@@ -483,7 +483,7 @@ static uint8_t imxrt_spi_build_insn_sequence(target_s *const target, const uint1
 				IMXRT_FLEXSPI_LUT_OPCODE(IMXRT_FLEXSPI_LUT_OP_READ) | IMXRT_FLEXSPI_LUT_MODE_SERIAL;
 		sequence[offset++].value = 0;
 	}
-	/* Because sequence gets 0 initalised above when it's declared, the STOP entry is already present */
+	/* Because sequence gets 0 initialised above when it's declared, the STOP entry is already present */
 	DEBUG_TARGET("Writing new instruction sequence to slot %u\n", slot);
 	for (size_t idx = 0; idx < 8U; ++idx)
 		DEBUG_TARGET("%zu: %02x %02x\n", idx, sequence[idx].opcode_mode, sequence[idx].value);
@@ -519,7 +519,7 @@ static void imxrt_spi_wait_complete(target_s *const target)
 		continue;
 	/* Then clear the interrupt bit it sets. */
 	target_mem_write32(target, IMXRT_FLEXSPI1_INT(priv), IMXRT_FLEXSPI1_INT_PRG_CMD_DONE);
-	/* Check if any errors occured */
+	/* Check if any errors occurred */
 	if (target_mem_read32(target, IMXRT_FLEXSPI1_INT(priv)) & IMXRT_FLEXSPI1_INT_CMD_ERR) {
 #if ENABLE_DEBUG == 1 && PC_HOSTED == 1
 		/* Read out the status code and display it */

src/target/jtag_scan.c

@@ -102,7 +102,7 @@ bool jtag_scan(void)
 		!jtag_read_irs())
 		return false;
 
-	/* IRs are all succesfully accounted for, so clean up and do housekeeping */
+	/* IRs are all successfully accounted for, so clean up and do housekeeping */
 	DEBUG_INFO("Return to Run-Test/Idle\n");
 	jtag_proc.jtagtap_next(true, true);
 	jtagtap_return_idle(1);
@@ -171,7 +171,7 @@ static bool jtag_read_idcodes(void)
 		/* If the IDCode read is all 1's, we've reached the end */
 		if (idcode == 0xffffffffU)
 			break;
-		/* Check if the max suported chain length is exceeded */
+		/* Check if the max supported chain length is exceeded */
 		if (device == JTAG_MAX_DEVS) {
 			DEBUG_ERROR("jtag_scan: Maximum chain length exceeded\n");
 			jtag_dev_count = 0;

src/target/lpc43xx.c

@@ -657,7 +657,7 @@ static bool lpc43x0_attach(target_s *const target)
 		 * If the boot source is anything other than SPI and the image contains no header,
 		 * the chip sets switches execution to that boot source.
 		 *
-		 * This process is laid out in Chaper 5 of UM10503. See Fig 16 on pg 59 for a more detailed view.
+		 * This process is laid out in Chapter 5 of UM10503. See Fig 16 on pg 59 for a more detailed view.
 		 */
 		lpc43x0_determine_flash_interface(target);
 	}

src/target/lpc_common.c

@@ -154,7 +154,7 @@ iap_status_e lpc_iap_call(lpc_flash_s *const flash, iap_result_s *const result,
 	if (flash->wdt_kick)
 		flash->wdt_kick(target);
 
-	/* Save IAP RAM and target regsiters to restore after IAP call */
+	/* Save IAP RAM and target registers to restore after IAP call */
 	iap_frame_s saved_frame;
 	/*
 	 * Note, we allocate space for the float regs even if the CPU doesn't implement them.
@@ -226,7 +226,7 @@ iap_status_e lpc_iap_call(lpc_flash_s *const flash, iap_result_s *const result,
 		}
 	}
 
-	/* Check if a fault occured while executing the call */
+	/* Check if a fault occurred while executing the call */
 	uint32_t status = 0;
 	target_reg_read(target, CORTEX_REG_XPSR, &status, sizeof(status));
 	if (status & CORTEXM_XPSR_EXCEPTION_MASK) {

src/target/msp432e4.c

@@ -25,7 +25,7 @@
  * This file implements MSP432 target specific functions for detecting
  * the device, providing the XML memory map and Flash memory programming.
  *
- * Refereces:
+ * References:
  * TI doc - SLAU723a
  *   MSP423e4xx Technical Reference Manual (https://www.ti.com/lit/ug/slau723a/slau723a.pdf)
  */

src/target/riscv32.c

@@ -607,7 +607,7 @@ void riscv32_mem_write(target_s *const target, const target_addr_t dest, const v
  * The following can be used as a key for understanding the various return results from the breakwatch functions:
  * 0 -> success
  * 1 -> not supported
- * -1 -> an error occured
+ * -1 -> an error occurred
  */
 
 static int riscv32_breakwatch_set(target_s *const target, breakwatch_s *const breakwatch)