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Fix: proper IR quirk handling for Xilinx FPGAs #1572

Fix: proper IR quirk handling for Xilinx FPGAs

Fix: proper IR quirk handling for Xilinx FPGAs #1572

Triggered via pull request October 29, 2023 22:16
Status Cancelled
Total duration 53s
Artifacts

build-pr.yml

on: pull_request
size-diff
31s
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Matrix: build-linux
Matrix: build-windows-mingw
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10 errors
build-mingw (windows-2022, clang64)
Canceling since a higher priority waiting request for 'build PR--refs/pull/1620/merge' exists
build-mingw (windows-2022, clang64)
The operation was canceled.
build-mingw (windows-2022, ucrt64)
Canceling since a higher priority waiting request for 'build PR--refs/pull/1620/merge' exists
build-mingw (windows-2022, ucrt64)
The operation was canceled.
size-diff
Canceling since a higher priority waiting request for 'build PR--refs/pull/1620/merge' exists
size-diff
The operation was canceled.
build-linux (ubuntu-20.04, focal, clang-15, 12.2.Rel1)
Canceling since a higher priority waiting request for 'build PR--refs/pull/1620/merge' exists
build-linux (ubuntu-20.04, focal, clang-15, 12.2.Rel1)
The operation was canceled.
build-linux (ubuntu-20.04, focal, gcc-11, 12.2.Rel1)
Canceling since a higher priority waiting request for 'build PR--refs/pull/1620/merge' exists
build-linux (ubuntu-20.04, focal, gcc-11, 12.2.Rel1)
The operation was canceled.