Skip to content

Fix: proper IR quirk handling for Xilinx FPGAs #1515

Fix: proper IR quirk handling for Xilinx FPGAs

Fix: proper IR quirk handling for Xilinx FPGAs #1515

Triggered via pull request September 23, 2023 23:52
Status Success
Total duration 5m 10s
Artifacts
This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

build-pr.yml

on: pull_request
size-diff
52s
size-diff
Matrix: build-linux
Matrix: build-windows-mingw
Fit to window
Zoom out
Zoom in