Skip to content
lint

Fix: proper IR quirk handling for Xilinx FPGAs #1175

Sign in to view logs

Fix: proper IR quirk handling for Xilinx FPGAs

Fix: proper IR quirk handling for Xilinx FPGAs #1175

Triggered via pull request September 23, 2023 23:52
@lethalbitlethalbit
synchronize #1620
lethalbit:aki/xilinx
Status Success
Total duration 26s
Artifacts –
This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

lint.yml

on: pull_request
pre-commit
15s
pre-commit
Fit to window
Zoom out
Zoom in