Skip to content

Fix: proper IR quirk handling for Xilinx FPGAs #1129

Fix: proper IR quirk handling for Xilinx FPGAs

Fix: proper IR quirk handling for Xilinx FPGAs #1129

Re-run triggered September 10, 2023 12:16
Status Success
Total duration 39s
Artifacts
This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

lint.yml

on: pull_request
pre-commit
pre-commit
Fit to window
Zoom out
Zoom in