Enable headless mode on RISC-V (adoptium#4935)

babsingh · Dec 28, 2023 · c5e7de8 · c5e7de8
1 parent e37ba10
commit c5e7de8
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/openjdk/openjdk.mk b/openjdk/openjdk.mk
@@ -16,6 +16,7 @@ NPROCS:=1
 MEMORY_SIZE:=1024
 
 OS:=$(shell uname -s)
+ARCH:=$(shell uname -m)
 
 ifeq ($(OS),Linux)
 	NPROCS:=$(shell grep -c ^processor /proc/cpuinfo)
@@ -97,6 +98,11 @@ ifeq ($(libcVendor),musl)
 	JTREG_KEY_OPTIONS := -k:'!headful'
 	VMOPTION_HEADLESS := -Djava.awt.headless=true
 endif
+# RISC-V is built in headless mode for now. See https://github.com/adoptium/ci-jenkins-pipelines/pull/867
+ifeq ($(ARCH),riscv64)
+	JTREG_KEY_OPTIONS := -k:'!headful'
+	VMOPTION_HEADLESS := -Djava.awt.headless=true
+endif
 JTREG_BASIC_OPTIONS += $(JTREG_KEY_OPTIONS)
 
 # set JTREG_BASIC_OPTIONS value into a new parameter before adding EXTRA_JTREG_OPTIONS