Update test.py

Correct for first aux output update delay
b-etz · Sep 3, 2024 · fd47675 · fd47675
1 parent 3d500da
commit fd47675
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/test/test.py b/test/test.py
@@ -41,9 +41,9 @@ async def test_project(dut):
     # Keep testing the module by changing the input values, waiting for
     # one or more clock cycles, and asserting the expected output values.
     dut.uio_in.value = 0x02 # Send a dah first
-    await ClockCycles(dut.clk,100)
+    await ClockCycles(dut.clk,3000)
     dut.uio_in.value = 0x03 # Press the dit too (start iambic behavior)
-    await ClockCycles(dut.clk,1)
+    await ClockCycles(dut.clk,3000)
 
     assert dut.uo_out.value == 0x00
     assert dut.uio_oe.value == 0x3C