HAWQ-1853. aarch64 port changes

depends/libhdfs3/CMake/Options.cmake

@@ -1,6 +1,10 @@
 OPTION(ENABLE_COVERAGE "enable code coverage" OFF)
 OPTION(ENABLE_DEBUG "enable debug build" OFF)
-OPTION(ENABLE_SSE "enable SSE4.2 buildin function" ON)
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "(x86)|(X86)|(amd64)|(AMD64)")
+  OPTION(ENABLE_SSE "enable SSE4.2 buildin function" ON)
+else()
+  OPTION(ENABLE_SSE "enable SSE4.2 buildin function" OFF)
+endif()
 OPTION(ENABLE_FRAME_POINTER "enable frame pointer on 64bit system with flag -fno-omit-frame-pointer, on 32bit system, it is always enabled" ON)
 OPTION(ENABLE_LIBCPP "using libc++ instead of libstdc++, only valid for clang compiler" OFF)
 OPTION(ENABLE_BOOST "using boost instead of native compiler c++0x support" OFF)
@@ -21,6 +25,7 @@ ENDIF(ENABLE_DEBUG STREQUAL ON)
 
 SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-strict-aliasing")
 SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fno-strict-aliasing")
+SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=native")
 
 IF(ENABLE_COVERAGE STREQUAL ON)
     INCLUDE(CodeCoverage)

depends/libhdfs3/src/common/HWCrc32c.cpp

@@ -63,6 +63,43 @@ static inline uint32_t _mm_crc32_u8(uint32_t crc, uint8_t value) {
 
 #include <nmmintrin.h>
 
+#endif
+#elif (defined(__aarch64__) && defined(__ARM_FEATURE_CRC32))
+namespace Hdfs {
+namespace Internal {
+
+#if defined(__LP64__)
+static inline uint64_t _mm_crc32_u64(uint64_t crc, uint64_t value) {
+    __asm__ __volatile__("crc32cx %w[c], %w[c], %x[v]\n\t"
+                         : [c] "+r"(crc)
+                         : [v] "r"(value));
+    return crc;
+}
+#endif
+
+static inline uint32_t _mm_crc32_u16(uint32_t crc, uint16_t value) {
+    __asm__ __volatile__("crc32ch %w[c], %w[c], %w[v]\n\t"
+                         : [c] "+r"(crc)
+                         : [v] "r"(value));
+    return crc;
+}
+
+static inline uint32_t _mm_crc32_u32(uint32_t crc, uint32_t value) {
+    __asm__ __volatile__("crc32cw %w[c], %w[c], %w[v]\n\t"
+                         : [c] "+r"(crc)
+                         : [v] "r"(value));
+    return crc;
+}
+
+static inline uint32_t _mm_crc32_u8(uint32_t crc, uint8_t value) {
+    __asm__ __volatile__("crc32cb %w[c], %w[c], %w[v]\n\t"
+                         : [c] "+r"(crc)
+                         : [v] "r"(value));
+    return crc;
+}
+
+}
+}
 #endif
 
 namespace Hdfs {
@@ -77,6 +114,8 @@ bool HWCrc32c::available() {
      */
     __get_cpuid(1, &eax, &ebx, &ecx, &edx);
     return (ecx & (1 << 20)) != 0;
+#elif (defined(__aarch64__) && defined(__ARM_FEATURE_CRC32))
+    return true;
 #else
     return false;
 #endif
@@ -156,4 +195,3 @@ void HWCrc32c::updateInt64(const char * b, int len) {
 }
 }
 
-#endif /* _HDFS_LIBHDFS3_COMMON_HWCHECKSUM_H_ */