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Mio fpga#91

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olajep wants to merge 24 commits intoaolofsson:mainaolofsson/oh:mainfrom olajep:mio-fpgaolajep/oh:mio-fpgaCopy head branch name to clipboard

+2,283-35

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Commits on Jun 6, 2016

• oh_fifo_async: Error on invalid TARGET/PARAMETERS

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• mio: mio_regs: Fix width of status_reg and config_reg

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• mio: Add FPGA project

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• mio: fpga: Connect master AXI interface

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• mio: mrx_io: Make reset logic synthesizable

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• mio: Add axi_mio module

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• mio: Add parallella_mio module

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• mio: axi_mio: Fix wait signals

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• mio: axi_mio: Add static remapping to slave axi access

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• mio: axi_mio: Propagate TARGET to mio instance

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• mio: mio_dp: Propagate TARGET to mtx and mrx instances

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• xilibs: ip: IPs must be in separate directories

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• xilibs: Add fifo_async_128x32 IP

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• mio: fpga: Add fifo_async_128x32 to IP list

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• common: oh_fifo_async: Add fifo_async_128x32 instance for XILINX target

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• mio: axi_mio: Fix s_rr_access signal

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• mio: mio_regs: Allow writing to sticky status bits

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• mio: mio_regs: Add readback for status register

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• mio: dv: dut_mio: Support register reads

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• mio: mio_regs: Reset all bits of config register

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• mio: dv: Add test for register read

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• mio: axi_mio: Simplified but working version

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• mio: axi_mio: Connect rest of AXI master channels

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• mio: axi_mio: Drop io prefix for io signals

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