arm/cortex-a,r: replace cp15 instruct to macros align operation

This is continue work of apache#13486 Discussion here: apache#13486 (comment) 1. move cp15.h to arch public 2. replace cp15 instruct to macros align operation 3. add memory barrier to avoid compiler optimization Signed-off-by: chao an <[email protected]>
anchao · Sep 19, 2024 · c720e9e · c720e9e
1 parent 0561b55
commit c720e9e
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Showing 10 changed files with 68 additions and 65 deletions.
diff --git a/arch/arm/src/armv7-a/barriers.h → arch/arm/include/armv7-a/barriers.h b/arch/arm/src/armv7-a/barriers.h → arch/arm/include/armv7-a/barriers.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-a/barriers.h
+ * arch/arm/include/armv7-a/barriers.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

diff --git a/arch/arm/src/armv7-a/cp15.h → arch/arm/include/armv7-a/cp15.h b/arch/arm/src/armv7-a/cp15.h → arch/arm/include/armv7-a/cp15.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-a/cp15.h
+ * arch/arm/include/armv7-a/cp15.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h
@@ -36,6 +36,9 @@
 #  include <stdint.h>
 #endif
 
+#include "cp15.h"
+#include "barriers.h"
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
@@ -457,11 +460,8 @@ static inline_function int up_cpu_index(void)
 
   /* Read the Multiprocessor Affinity Register (MPIDR) */
 
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
-    : "=r"(mpidr)
-  );
+  ARM_ISB();
+  mpidr = CP15_GET(MPIDR);
 
   /* And return the CPU ID field */
 
@@ -500,23 +500,15 @@ static inline_function uint32_t up_getsp(void)
 noinstrument_function
 static inline_function uint32_t *up_current_regs(void)
 {
-  uint32_t *regs;
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    : "=r"(regs)
-  );
-  return regs;
+  ARM_ISB();
+  return (uint32_t *)CP15_GET(TPIDRPRW);
 }
 
 noinstrument_function
 static inline_function void up_set_current_regs(uint32_t *regs)
 {
-  __asm__ __volatile__
-  (
-    "mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    :: "r"(regs)
-  );
+  CP15_SET(TPIDRPRW, regs);
+  ARM_ISB();
 }
 
 noinstrument_function

diff --git a/arch/arm/src/armv7-r/barriers.h → arch/arm/include/armv7-r/barriers.h b/arch/arm/src/armv7-r/barriers.h → arch/arm/include/armv7-r/barriers.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-r/barriers.h
+ * arch/arm/include/armv7-r/barriers.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

diff --git a/arch/arm/src/armv7-r/cp15.h → arch/arm/include/armv7-r/cp15.h b/arch/arm/src/armv7-r/cp15.h → arch/arm/include/armv7-r/cp15.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-r/cp15.h
+ * arch/arm/include/armv7-r/cp15.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h
@@ -36,6 +36,9 @@
 #  include <stdint.h>
 #endif
 
+#include "cp15.h"
+#include "barriers.h"
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
@@ -357,7 +360,7 @@ static inline irqstate_t irqstate(void)
 
 /* Disable IRQs and return the previous IRQ state */
 
-static inline irqstate_t up_irq_save(void)
+noinstrument_function static inline irqstate_t up_irq_save(void)
 {
   unsigned int cpsr;
 
@@ -417,7 +420,7 @@ static inline irqstate_t up_irq_disable(void)
 
 /* Restore saved IRQ & FIQ state */
 
-static inline void up_irq_restore(irqstate_t flags)
+noinstrument_function static inline void up_irq_restore(irqstate_t flags)
 {
   __asm__ __volatile__
     (
@@ -452,11 +455,8 @@ static inline_function int up_cpu_index(void)
 
   /* Read the Multiprocessor Affinity Register (MPIDR) */
 
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
-    : "=r"(mpidr)
-  );
+  ARM_ISB();
+  mpidr = CP15_GET(MPIDR);
 
   /* And return the CPU ID field */
 
@@ -479,26 +479,31 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
+/****************************************************************************
+ * Name:
+ *   up_current_regs/up_set_current_regs
+ *
+ * Description:
+ *   We use the following code to manipulate the TPIDRPRW register,
+ *   which exists uniquely for each CPU and is primarily designed to store
+ *   current thread information. Currently, we leverage it to store interrupt
+ *   information, with plans to further optimize its use for storing both
+ *   thread and interrupt information in the future.
+ *
+ ****************************************************************************/
+
 noinstrument_function
 static inline_function uint32_t *up_current_regs(void)
 {
-  uint32_t *regs;
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    : "=r"(regs)
-  );
-  return regs;
+  ARM_ISB();
+  return (uint32_t *)CP15_GET(TPIDRPRW);
 }
 
 noinstrument_function
 static inline_function void up_set_current_regs(uint32_t *regs)
 {
-  __asm__ __volatile__
-  (
-    "mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    :: "r"(regs)
-  );
+  CP15_SET(TPIDRPRW, regs);
+  ARM_ISB();
 }
 
 noinstrument_function

diff --git a/arch/arm/src/armv8-r/barriers.h → arch/arm/include/armv8-r/barriers.h b/arch/arm/src/armv8-r/barriers.h → arch/arm/include/armv8-r/barriers.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv8-r/barriers.h
+ * arch/arm/include/armv8-r/barriers.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

diff --git a/arch/arm/src/armv8-r/cp15.h → arch/arm/include/armv8-r/cp15.h b/arch/arm/src/armv8-r/cp15.h → arch/arm/include/armv8-r/cp15.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv8-r/cp15.h
+ * arch/arm/include/armv8-r/cp15.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

diff --git a/arch/arm/include/armv8-r/irq.h b/arch/arm/include/armv8-r/irq.h
@@ -36,6 +36,9 @@
 #  include <stdint.h>
 #endif
 
+#include "cp15.h"
+#include "barriers.h"
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
@@ -357,7 +360,7 @@ static inline irqstate_t irqstate(void)
 
 /* Disable IRQs and return the previous IRQ state */
 
-static inline irqstate_t up_irq_save(void)
+noinstrument_function static inline irqstate_t up_irq_save(void)
 {
   unsigned int cpsr;
 
@@ -417,7 +420,7 @@ static inline irqstate_t up_irq_disable(void)
 
 /* Restore saved IRQ & FIQ state */
 
-static inline void up_irq_restore(irqstate_t flags)
+noinstrument_function static inline void up_irq_restore(irqstate_t flags)
 {
   __asm__ __volatile__
     (
@@ -452,11 +455,8 @@ static inline_function int up_cpu_index(void)
 
   /* Read the Multiprocessor Affinity Register (MPIDR) */
 
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
-    : "=r"(mpidr)
-  );
+  ARM_ISB();
+  mpidr = CP15_GET(MPIDR);
 
   /* And return the CPU ID field */
 
@@ -479,26 +479,31 @@ static inline_function uint32_t up_getsp(void)
   return sp;
 }
 
+/****************************************************************************
+ * Name:
+ *   up_current_regs/up_set_current_regs
+ *
+ * Description:
+ *   We use the following code to manipulate the TPIDRPRW register,
+ *   which exists uniquely for each CPU and is primarily designed to store
+ *   current thread information. Currently, we leverage it to store interrupt
+ *   information, with plans to further optimize its use for storing both
+ *   thread and interrupt information in the future.
+ *
+ ****************************************************************************/
+
 noinstrument_function
 static inline_function uint32_t *up_current_regs(void)
 {
-  uint32_t *regs;
-  __asm__ __volatile__
-  (
-    "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    : "=r"(regs)
-  );
-  return regs;
+  ARM_ISB();
+  return (uint32_t *)CP15_GET(TPIDRPRW);
 }
 
 noinstrument_function
 static inline_function void up_set_current_regs(uint32_t *regs)
 {
-  __asm__ __volatile__
-  (
-    "mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
-    :: "r"(regs)
-  );
+  CP15_SET(TPIDRPRW, regs);
+  ARM_ISB();
 }
 
 noinstrument_function

diff --git a/arch/arm/src/Makefile b/arch/arm/src/Makefile
@@ -37,11 +37,12 @@ else                                    # ARM9, ARM7TDMI, etc.
 ARCH_SUBDIR = arm
 endif
 
-ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)
 
-INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip
-INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common
-INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR)
+INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)src$(DELIM)chip
+INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)src$(DELIM)common
+INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)src$(DELIM)$(ARCH_SUBDIR)
+INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)include$(DELIM)$(ARCH_SUBDIR)
 INCLUDES += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)sched
 
 CPPFLAGS += $(INCLUDES)