arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|

Squashed: Initial settings for MCPWM Capture on board level Created lower half files - compilation ok Using capture debug features. Simple example on fops works Successful duty and freq calculation Documentation update Fixed and added interupt capabilities for all 3 capture channels Cleaned defconfig Renamed macros, added S3 options and moved arch source to common dir Added support for ESP32S3 Added capture example to defconfig and renamed
anchao · Jun 27, 2024 · 365e9e9 · 365e9e9
1 parent 92747b7
commit 365e9e9
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Showing 22 changed files with 1,453 additions and 2 deletions.
diff --git a/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst b/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst
@@ -294,6 +294,22 @@ the ``buttons`` application and pressing on any of the available board buttons::
     nsh> Sample = 1
     Sample = 0
 
+capture
+--------
+
+The capture configuration enables the capture driver and the capture example, allowing
+the user to measure duty cycle and frequency of a signal. Default pin is GPIO 14 with
+an internal pull-up resistor enabled. When connecting a 50 Hz pulse with 50% duty cycle,
+the following output is expected:
+
+nsh> cap
+cap_main: Hardware initialized. Opening the capture device: /dev/capture0
+cap_main: Number of samples: 0
+pwm duty cycle: 50 % 
+pwm frequence: 50 Hz 
+pwm duty cycle: 50 % 
+pwm frequence: 50 Hz 
+
 coremark
 --------
 

diff --git a/Documentation/platforms/xtensa/esp32/index.rst b/Documentation/platforms/xtensa/esp32/index.rst
@@ -173,7 +173,7 @@ GPIO         Yes
 I2C          Yes
 I2S          Yes
 LED_PWM      Yes
-MCPWM        No
+MCPWM        Yes    Capture
 Pulse_CNT    No
 RMT          Yes
 RNG          Yes

diff --git a/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst b/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst
@@ -146,6 +146,22 @@ the ``buttons`` application and pressing on any of the available board buttons::
     nsh> Sample = 1
     Sample = 0
 
+capture
+--------
+
+The capture configuration enables the capture driver and the capture example, allowing
+the user to measure duty cycle and frequency of a signal. Default pin is GPIO 12 with
+an internal pull-up resistor enabled. When connecting a 50 Hz pulse with 50% duty cycle,
+the following output is expected:
+
+nsh> cap
+cap_main: Hardware initialized. Opening the capture device: /dev/capture0
+cap_main: Number of samples: 0
+pwm duty cycle: 50 % 
+pwm frequence: 50 Hz 
+pwm duty cycle: 50 % 
+pwm frequence: 50 Hz 
+
 coremark
 --------
 

diff --git a/Documentation/platforms/xtensa/esp32s3/index.rst b/Documentation/platforms/xtensa/esp32s3/index.rst
@@ -178,7 +178,7 @@ I2C          No
 I2S          Yes
 LCD          No
 LED_PWM      No
-MCPWM        No
+MCPWM        Yes    Capture
 Pulse_CNT    No
 RMT          No
 RNG          No

diff --git a/arch/xtensa/src/common/espressif/Kconfig b/arch/xtensa/src/common/espressif/Kconfig
@@ -7,3 +7,11 @@ config ESP_RMT
 		an infrared transceiver. However, due to the flexibility of its data
 		format, RMT can be extended to a versatile and general-purpose
 		transceiver, transmitting or receiving many other types of signals.
+
+config ESP_MCPWM
+	bool "Motor Control PWM (MCPWM)"
+	default n
+	depends on ARCH_CHIP_ESP32 || ARCH_CHIP_ESP32S3
+	---help---
+		Enable support for timer capture and motor control using
+		the Motor Control PWM peripheral.
diff --git a/arch/xtensa/src/common/espressif/Make.defs b/arch/xtensa/src/common/espressif/Make.defs
@@ -25,4 +25,8 @@ CHIP_CSRCS += esp_ws2812.c
 endif
 endif
 
+ifeq ($(CONFIG_ESP_MCPWM),y)
+CHIP_CSRCS += esp_mcpwm.c
+endif
+
 INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif$(DELIM)platform_include