Add support for file list files

Signed-off-by: Alex Forencich <[email protected]>
alexforencich · Aug 6, 2024 · 664ab9f · 664ab9f
1 parent c1c3dc0
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Showing 24 changed files with 207 additions and 48 deletions.
diff --git a/rtl/axis_arb_mux.f b/rtl/axis_arb_mux.f
@@ -0,0 +1,3 @@
+axis_arb_mux.v
+arbiter.v
+priority_encoder.v
diff --git a/rtl/axis_async_fifo_adapter.f b/rtl/axis_async_fifo_adapter.f
@@ -0,0 +1,3 @@
+axis_async_fifo_adapter.v
+axis_async_fifo.v
+axis_adapter.v
diff --git a/rtl/axis_cobs_encode.f b/rtl/axis_cobs_encode.f
@@ -0,0 +1,2 @@
+axis_cobs_encode.v
+axis_fifo.v
diff --git a/rtl/axis_fifo_adapter.f b/rtl/axis_fifo_adapter.f
@@ -0,0 +1,3 @@
+axis_fifo_adapter.v
+axis_fifo.v
+axis_adapter.v
diff --git a/rtl/axis_frame_length_adjust_fifo.f b/rtl/axis_frame_length_adjust_fifo.f
@@ -0,0 +1,3 @@
+axis_frame_length_adjust_fifo.v
+axis_frame_length_adjust.v
+axis_fifo.v
diff --git a/rtl/axis_pipeline_register.f b/rtl/axis_pipeline_register.f
@@ -0,0 +1,2 @@
+axis_pipeline_register.v
+axis_register.v
diff --git a/rtl/axis_ram_switch.f b/rtl/axis_ram_switch.f
@@ -0,0 +1,4 @@
+axis_ram_switch.v
+axis_adapter.v
+arbiter.v
+priority_encoder.v
diff --git a/rtl/axis_switch.f b/rtl/axis_switch.f
@@ -0,0 +1,4 @@
+axis_switch.v
+axis_register.v
+arbiter.v
+priority_encoder.v
diff --git a/tb/axis_arb_mux/Makefile b/tb/axis_arb_mux/Makefile
@@ -33,9 +33,13 @@ WRAPPER  = $(DUT)_wrap_$(PORTS)
 TOPLEVEL = $(WRAPPER)
 MODULE   = test_$(DUT)
 VERILOG_SOURCES += $(WRAPPER).v
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/arbiter.v
-VERILOG_SOURCES += ../../rtl/priority_encoder.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_DATA_WIDTH := 8

diff --git a/tb/axis_arb_mux/test_axis_arb_mux.py b/tb/axis_arb_mux/test_axis_arb_mux.py
@@ -316,6 +316,19 @@ def incrementing_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize("round_robin", [0, 1])
 @pytest.mark.parametrize("data_width", [8, 16, 32])
 @pytest.mark.parametrize("ports", [1, 4])
@@ -335,11 +348,11 @@ def test_axis_arb_mux(request, ports, data_width, round_robin):
 
     verilog_sources = [
         wrapper_file,
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "arbiter.v"),
-        os.path.join(rtl_dir, "priority_encoder.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['DATA_WIDTH'] = data_width

diff --git a/tb/axis_async_fifo_adapter/Makefile b/tb/axis_async_fifo_adapter/Makefile
@@ -29,9 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 DUT      = axis_async_fifo_adapter
 TOPLEVEL = $(DUT)
 MODULE   = test_$(DUT)
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/axis_async_fifo.v
-VERILOG_SOURCES += ../../rtl/axis_adapter.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_S_DATA_WIDTH := 8

diff --git a/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
@@ -662,6 +662,19 @@ def incrementing_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
     "drop_when_full", "mark_when_full"),
     [(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
@@ -676,11 +689,11 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width,
     toplevel = dut
 
     verilog_sources = [
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "axis_async_fifo.v"),
-        os.path.join(rtl_dir, "axis_adapter.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['S_DATA_WIDTH'] = s_data_width

diff --git a/tb/axis_cobs_encode/Makefile b/tb/axis_cobs_encode/Makefile
@@ -29,8 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 DUT      = axis_cobs_encode
 TOPLEVEL = $(DUT)
 MODULE   = test_$(DUT)
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/axis_fifo.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_APPEND_ZERO := 0

diff --git a/tb/axis_cobs_encode/test_axis_cobs_encode.py b/tb/axis_cobs_encode/test_axis_cobs_encode.py
@@ -217,17 +217,31 @@ def prbs_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize("append_zero", [0, 1])
 def test_axis_cobs_encode(request, append_zero):
     dut = "axis_cobs_encode"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
 
     verilog_sources = [
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "axis_fifo.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['APPEND_ZERO'] = append_zero

diff --git a/tb/axis_fifo_adapter/Makefile b/tb/axis_fifo_adapter/Makefile
@@ -29,9 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 DUT      = axis_fifo_adapter
 TOPLEVEL = $(DUT)
 MODULE   = test_$(DUT)
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/axis_fifo.v
-VERILOG_SOURCES += ../../rtl/axis_adapter.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_S_DATA_WIDTH := 8

diff --git a/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
@@ -445,6 +445,19 @@ def incrementing_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
     "drop_when_full", "mark_when_full"),
     [(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
@@ -459,11 +472,11 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width,
     toplevel = dut
 
     verilog_sources = [
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "axis_fifo.v"),
-        os.path.join(rtl_dir, "axis_adapter.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['S_DATA_WIDTH'] = s_data_width

diff --git a/tb/axis_frame_length_adjust_fifo/Makefile b/tb/axis_frame_length_adjust_fifo/Makefile
@@ -29,9 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 DUT      = axis_frame_length_adjust_fifo
 TOPLEVEL = $(DUT)
 MODULE   = test_$(DUT)
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/axis_frame_length_adjust.v
-VERILOG_SOURCES += ../../rtl/axis_fifo.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_DATA_WIDTH := 8

diff --git a/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py b/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
@@ -290,18 +290,31 @@ def incrementing_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize("data_width", [8, 16, 32])
 def test_axis_frame_length_adjust_fifo(request, data_width):
     dut = "axis_frame_length_adjust_fifo"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
 
     verilog_sources = [
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, f"axis_frame_length_adjust.v"),
-        os.path.join(rtl_dir, f"axis_fifo.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['DATA_WIDTH'] = data_width

diff --git a/tb/axis_pipeline_register/Makefile b/tb/axis_pipeline_register/Makefile
@@ -29,8 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 DUT      = axis_pipeline_register
 TOPLEVEL = $(DUT)
 MODULE   = test_$(DUT)
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/axis_register.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_DATA_WIDTH := 8

diff --git a/tb/axis_pipeline_register/test_axis_pipeline_register.py b/tb/axis_pipeline_register/test_axis_pipeline_register.py
@@ -212,6 +212,19 @@ def incrementing_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize("reg_type", [0, 1, 2])
 @pytest.mark.parametrize("data_width", [8, 16, 32])
 @pytest.mark.parametrize("length", [0, 1, 2])
@@ -221,10 +234,11 @@ def test_axis_pipeline_register(request, length, data_width, reg_type):
     toplevel = dut
 
     verilog_sources = [
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "axis_register.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['DATA_WIDTH'] = data_width

diff --git a/tb/axis_ram_switch/Makefile b/tb/axis_ram_switch/Makefile
@@ -34,10 +34,13 @@ WRAPPER  = $(DUT)_wrap_$(S_COUNT)x$(M_COUNT)
 TOPLEVEL = $(WRAPPER)
 MODULE   = test_$(DUT)
 VERILOG_SOURCES += $(WRAPPER).v
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/axis_adapter.v
-VERILOG_SOURCES += ../../rtl/arbiter.v
-VERILOG_SOURCES += ../../rtl/priority_encoder.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_FIFO_DEPTH := 4096

diff --git a/tb/axis_ram_switch/test_axis_ram_switch.py b/tb/axis_ram_switch/test_axis_ram_switch.py
@@ -323,6 +323,19 @@ def incrementing_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize("m_data_width", [8, 32])
 @pytest.mark.parametrize("s_data_width", [8, 32])
 @pytest.mark.parametrize("m_count", [1, 4])
@@ -343,12 +356,11 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width):
 
     verilog_sources = [
         wrapper_file,
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "axis_adapter.v"),
-        os.path.join(rtl_dir, "arbiter.v"),
-        os.path.join(rtl_dir, "priority_encoder.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['FIFO_DEPTH'] = 4096