ENEE 759 U Project

Final Project Instructions

./BDDs >>> Including packages built on CUDD 2.5; converting BLIF (AIG) into BDDs w.r.t to input variable order defined in BLIF

./auto-pipelin >>> Including examples and benchmarks (in verilog) of Boolean-level auto-pipelining using retiming; evaluation flow included

./scheduling >>> Including DFGs represented in edgelist format with memory usages indicated on edge weights (weighted DAGs)