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Add Optimization Barriers #4763
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Add Optimization Barriers #4763
georgerennie
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YosysHQ:main
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georgerennie:george/optimization_barriers
Commits on Nov 20, 2024
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* This acts as an optimization barrier, limiting the rewriting allowed * For now this forbids all optimization, but attributes can be added to opt in to specific optimizations as required
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* This uses $barrier optimization barriers to connect wires into the flattened module instead of connections
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optbarriers: add command to add/remove optimization barriers
* This can optionally ignore rewriting the outputs of cells or processes * This by default rewrites drivers of wires with public names but can also optionally rewrite drivers of wires with private names * A -remove flag allows cleaning up the design by replacing barriers with connections
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* This uses optbarriers and flatten -barriers to insert barriers on public wires in the design, limiting the optimization that can affect them
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