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Adjust keep_hierarchy behavior #4706

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@povik povik commented Nov 5, 2024

What are the reasons/motivation for this change?

This makes two changes to keep_hierarchy -min_cost to make it better suited to the task of partially preserving hierarchy for macro placement:

  • Don't count cost from submodules marked with keep_hierarchy towards the upper module's cost.
  • Accept a gate_cost_equivalent attribute as a way of specifying cost on blackboxes.

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povik commented Nov 5, 2024

There's still a bit of a disconnect with the -min_cost cost model being for the number of gates post initial mapping to fine cell, but for the macro placement use case the size of the module at the end of synthesis is more relevant. This is something to address later.

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number of gates post initial mapping to fine cell, but for the macro placement use case the size of the module at the end of synthesis is more relevant

When I built this I experimented with also running opt in the flow and it didn't make much of a difference vs just techmapping, so I think this may not be as much of a problem? Anyway, it's just a knob for the user to twiddle, and users with an engineering background (the core audience) usually like that kind of arbitrary control, even if to a fault

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povik commented Nov 11, 2024

For instance numbers I expect opt isn’t as important as the abc transformations and mapping to technology cells

@@ -23,20 +23,77 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct ThresholdHiearchyKeeping {
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nit: Hiearchy -> Hierarchy

@@ -575,6 +575,9 @@ Non-standard or SystemVerilog features for formal verification
``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
is marked with the ``(* gclk *)`` Verilog attribute.

- The `gate_cost_equivalent` attribute on a module can be used to specify
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This chapter is "Non-standard or SystemVerilog features for formal verification", shouldn't it go into the preceding one?

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Maybe we could direct readers to check the keep_hierarchy help string?

log(" gates after simple techmapping. Intended for tuning trade-offs between\n");
log(" quality and yosys runtime.\n");
log("\n");
log(" When evaluating a module's cost, gates which are within a submodule\n");
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It seems like modules already labeled keep_hierarchy before this pass would still contribute to their supermodule's sum cost

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