Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

ast: Substitute rvalues when parsing out print arguments #3918

Merged
merged 1 commit into from
Sep 11, 2023

Conversation

povik
Copy link
Member

@povik povik commented Sep 5, 2023

Apply the local substitutions stemming from process context when parsing out format arguments to $display or other statements.

This is to fix #3917.

Apply the local substitutions stemming from process context when parsing
out format arguments to `$display` or other statements.
@@ -759,7 +759,7 @@ struct AST_INTERNAL::ProcessGenerator
arg.realtime = true;
} else {
arg.type = VerilogFmtArg::INTEGER;
arg.sig = node->genRTLIL();
arg.sig = node->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This is all that seems to need change. It introduces an extra call to detectSignWidthWorker from within genWidthRTLIL which hopefully is benign.

@povik povik merged commit 31ee566 into YosysHQ:master Sep 11, 2023
15 checks passed
@povik povik deleted the print-sampling-fix branch October 9, 2023 09:55
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

$print cells converted from $display tasks don't sample signals according to Verilog semantics
2 participants