Preliminary fixes, not done

YosysHQ · Nov 17, 2024 · ee18e1f · ee18e1f
1 parent a3cc228
commit ee18e1f
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Showing 2 changed files with 13 additions and 12 deletions.
diff --git a/passes/pmgen/peepopt_muldiv_c.pmg b/passes/pmgen/peepopt_muldiv_c.pmg
@@ -19,9 +19,8 @@ code a b_const mul_y
 	mul_y = port(mul, \Y);
 
 	// Fanout of each multiplier Y bit should be 1 (no bit-split)
-	for (auto bit : mul_y)
-		if (nusers(bit) != 2)
-			reject;
+	if (nusers(mul_y) != 2)
+		reject;
 
 	// A and B can be interchanged
 	branch;

diff --git a/passes/pmgen/peepopt_muxadd.pmg b/passes/pmgen/peepopt_muxadd.pmg
@@ -6,17 +6,19 @@ pattern muxadd
 //
 
 state <SigSpec> add_a add_b add_y
+state <bool> add_a_signed
+state <IdString> add_a_id
 
 match add
 	// Select adder
 	select add->type == $add
 	choice <IdString> A {\A, \B}
-        define <IdString> B (A == \A ? \B : \A)
-        set add_y port(add, \Y)
-        set add_a port(add, A)
-        set add_b port(add, B)
-        set add_a_signed param(add, (A == \A) ? \A_SIGNED : \B_SIGNED))
-        set add_a_id A
+	define <IdString> B (A == \A ? \B : \A)
+	set add_y port(add, \Y)
+	set add_a port(add, A)
+	set add_b port(add, B)
+	set add_a_signed param(add, (A == \A) ? \A_SIGNED : \B_SIGNED)
+	set add_a_id A
 endmatch
 
 code add_y add_a add_b
@@ -26,8 +28,8 @@ code add_y add_a add_b
 	add_y = port(add, \Y);
 
 	// Fanout of each adder Y bit should be 1 (no bit-split)
-        if (nusers(add_y) != 2)
-            reject;
+	if (nusers(add_y) != 2)
+		reject;
 
 	// A and B can be interchanged
 	branch;
@@ -37,7 +39,7 @@ endcode
 match mux
 	// Select mux of form s ? (a + b) : a, allow leading 0s when A_WIDTH != Y_WIDTH
 	select mux->type == $mux
-	index <SigSpec> port(mux, \A) === SigSpec({Const(State::S0, GetSize(add_y)-GetSize(add_a)), add_a})
+	index <SigSpec> port(mux, \A) === SigSpec({Const(!param(add, \A_SIGNED).bool() ? () : State::S0, GetSize(add_y)-GetSize(add_a)), add_a})
 	index <SigSpec> port(mux, \B) === add_y
 endmatch