Enable synth_ecp5 wrapper and copy sim files for backwards compatibility

Makefile

@@ -575,6 +575,13 @@ $(subst //,/,$(1)/$(notdir $(2))): $(2)
 	$$(Q) cp "$(YOSYS_SRC)"/$(2) $(subst //,/,$(1)/$(notdir $(2)))
 endef
 
+define add_share_file_and_rename
+EXTRA_TARGETS += $(subst //,/,$(1)/$(3))
+$(subst //,/,$(1)/$(3)): $(2)
+	$$(P) mkdir -p $(1)
+	$$(Q) cp "$(YOSYS_SRC)"/$(2) $(subst //,/,$(1)/$(3))
+endef
+
 define add_gen_share_file
 EXTRA_TARGETS += $(subst //,/,$(1)/$(notdir $(2)))
 $(subst //,/,$(1)/$(notdir $(2))): $(2)

techlibs/lattice/Makefile.inc

@@ -25,3 +25,11 @@ $(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
 $(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
 $(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
 $(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))
+
+
+$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_ff.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_io.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/lattice/common_sim.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/lattice/ccu2c_sim.vh))
+$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_sim_ecp5.v,cells_sim.v))
+$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_bb_ecp5.v,cells_bb.v))

techlibs/lattice/synth_lattice.cc

@@ -483,7 +483,6 @@ struct SynthLatticePass : public ScriptPass
 	}
 } SynthLatticePass;
 
-/*
 struct SynthEcp5Pass : public Pass
 {
 	SynthEcp5Pass() : Pass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
@@ -498,6 +497,5 @@ struct SynthEcp5Pass : public Pass
 		Pass::call(design, args);
 	}
 } SynthEcp5Pass;
-*/
 
 PRIVATE_NAMESPACE_END