Merge pull request #4723 from povik/memv2-nordports

rtlil: Adjust internal check for `$mem_v2` cells
YosysHQ · Nov 18, 2024 · 270846a · 270846a
2 parents 1cb5fd0 + e82e5f8
commit 270846a
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Showing 2 changed files with 12 additions and 3 deletions.
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
@@ -1856,9 +1856,9 @@ namespace {
 				param_bits(ID::RD_COLLISION_X_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
 				param_bits(ID::RD_WIDE_CONTINUATION, max(1, param(ID::RD_PORTS)));
 				param_bits(ID::RD_CE_OVER_SRST, max(1, param(ID::RD_PORTS)));
-				param_bits(ID::RD_ARST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
-				param_bits(ID::RD_SRST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
-				param_bits(ID::RD_INIT_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
+				param_bits(ID::RD_ARST_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
+				param_bits(ID::RD_SRST_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
+				param_bits(ID::RD_INIT_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
 				param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
 				param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
 				param_bits(ID::WR_WIDE_CONTINUATION, max(1, param(ID::WR_PORTS)));

diff --git a/tests/memories/nordports.ys b/tests/memories/nordports.ys
@@ -0,0 +1,9 @@
+# check memory_collect doesn't produce invalid RTLIL on a memory w/o read ports
+read_rtlil <<EOF
+autoidx 1
+attribute \top 1
+module \top
+  memory width 4 size 3 \foo
+end
+EOF
+memory_collect