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Add B extension (Zba, Zbb, Zbs) #29

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Add B extension (Zba, Zbb, Zbs) #29

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Includes updated NERV demonstrator.

@KrystalDelusion
B extension starts with Zba
38d171d 
- Update `insn_shimm` and `insn_alu` to support unsigned words (`uwmode`). This
  is used when the result is of width XLEN but the lower 32 bits from one of the
  inputs (rs1) is zero-extended.
- Update `isa_propagate` to match multi-letter extensions e.g. `Zba`.
- Add Zba instructions and the beginnings of the rest of the B extension.
@KrystalDelusion
Next comes Zbb
9c356b4 
- Add B-type format.
- Implement (most) Zbb instructions.
- Add `insnt_count` and `insn_ext` for bit count and extension instructions.
- Be unconvinced that the count checks will work as intended.
- Be confused about `orc_b` and `rev8` instructions and leave them commented out for now.
@KrystalDelusion
Zbs
85096dc 
- Add bitwise variation on R-type instruction format.
- Add `insn_bit` function for bitwise functions in Zbs extension.
- Add Zbs instructions.
@KrystalDelusion
Bug squashing b extension
beef78c
@KrystalDelusion
WIP b extension for NERV
06e3608 
Everything but `clz` `ctz` and `cpop` should work.
@KrystalDelusion
Drop pseudo instruction zext.w
3b2b119
@KrystalDelusion
Fix ctz and clz
84c3acc
@KrystalDelusion
rev8 and orc_b instructions
845d3bb
@KrystalDelusion
Add extra Zbb instructions
bc815ca 
CLZ, CTZ, CPOP, ORC.B, and REV8.
@KrystalDelusion
Fixing some 64 bit instructions
c00c768
@KrystalDelusion
Disable csr spec tests
fb3b7a8 
Having the csr_spec option enables CSR testing, including the misa CSR which uses the define `RISCV_FORMAL_CSR_MISA`.  If the CSR_MISA flag is defined then instructions from extensions will check the misa CSR includes the bit flag for the instruction.  We don't want that, since NERV misa is all zeros.
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@KrystalDelusion