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CascadeFlowOp and ConfigureCascadeOp #974

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751a78e
Add new ConfigureCascadeOp and CascadeDir attribute to AIE dialect. A…
abisca Feb 2, 2024
dbe8e72
Update lib/Dialect/AIE/IR/AIEDialect.cpp
AndraBisca Feb 2, 2024
4bfae99
Update lib/Dialect/AIE/IR/AIEDialect.cpp
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ce318fd
Update aie2 cascade unit test
abisca Feb 5, 2024
8c136ca
Add cascade config to ipu target.
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58d49ce
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cascad…
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2c022b7
Merge branch 'cascade-config' of https://github.com/Xilinx/mlir-aie i…
abisca Feb 5, 2024
54afbc6
Update lib/Targets/AIETargetCDODirect.cpp
AndraBisca Feb 5, 2024
85754d6
Update test/unit_tests/aie2/03_cascade_core_functions/test.cpp
AndraBisca Feb 5, 2024
5b296d2
Replace dyn_cast with cast, where applicable.
abisca Feb 6, 2024
ab8e696
Fix merge conflicts
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5908d8a
Restructure AIEAttr.td
abisca Feb 6, 2024
d263910
Modify CDO and Airbin targets.
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d06465e
Update lib/Targets/AIETargetAirbin.cpp
AndraBisca Feb 6, 2024
20267f9
Update lib/Targets/AIETargetCDODirect.cpp
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40858b0
Add ipu test
abisca Feb 6, 2024
5b42283
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cascad…
abisca Feb 6, 2024
7147c38
Update test with AIE2 locks
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29376c7
Fix lock value
abisca Feb 7, 2024
4c9fffa
Add Makefile to configure_cascade test
abisca Feb 8, 2024
8424030
Add CMakeLists to configure_cascade
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7da8bb1
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cascad…
abisca Feb 8, 2024
717ee26
Make cascade ipu test more complex
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df5e668
cleanup design
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cfa1b45
Update test/ipu-xrt/configure_cascade/test.cpp
AndraBisca Feb 8, 2024
9ce7213
Update test/ipu-xrt/configure_cascade/test.cpp
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4e6bd1e
Remove locks
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bd995bd
Merge branch 'cascade-config' of https://github.com/Xilinx/mlir-aie i…
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757b761
Fix run.lit
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697d30f
Delete ConfigureCascadeOp and replace with CascadeFlowOp and CascadeS…
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1049a22
Resolve conflicts with main
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53e2420
Update include/aie/Dialect/AIE/Transforms/AIEPasses.h
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Update lib/Dialect/AIE/IR/AIEDialect.cpp
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Update lib/Dialect/AIE/IR/AIEDialect.cpp
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Update lib/Dialect/AIE/IR/AIEDialect.cpp
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a0c37b2
Update lib/Dialect/AIE/IR/AIEDialect.cpp
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ef537f4
Update lib/Dialect/AIE/Transforms/AIELowerCascadeFlows.cpp
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dded7d7
Update lib/Targets/AIETargetAirbin.cpp
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Update lib/Targets/AIETargetAirbin.cpp
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18aaca8
Update lib/Dialect/AIE/Transforms/AIELowerCascadeFlows.cpp
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Update lib/Dialect/AIE/Transforms/AIELowerCascadeFlows.cpp
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Update lib/Dialect/AIE/Transforms/AIELowerCascadeFlows.cpp
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Update lib/Dialect/AIE/Transforms/AIELowerCascadeFlows.cpp
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Update lib/Dialect/AIE/Transforms/AIELowerCascadeFlows.cpp
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4225380
Update lib/Targets/AIETargetCDODirect.cpp
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e716656
Clang format
abisca Feb 13, 2024
e2ccfb3
Resolve conflicts
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32a3de5
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cascad…
abisca Feb 13, 2024
1ddf679
Add tests for memtiles and shimtiles
abisca Feb 13, 2024
799a1d6
Fix issue of cascade_flow lowering to cascade switchboxes with multip…
abisca Feb 13, 2024
98d71aa
Enable cascade lowering in aiecc
abisca Feb 14, 2024
9964026
Rename cascade ipu test
abisca Feb 14, 2024
2adebaf
Rename test target
abisca Feb 14, 2024
3217670
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cascad…
abisca Feb 14, 2024
8b8041f
Replace CascadeSwitchboxOp with previously deprecated ConfigureCascad…
abisca Feb 15, 2024
ecc276b
Add extra tile checks to ConfigureCascadeOp verify()
abisca Feb 15, 2024
0b647d5
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cascad…
abisca Feb 15, 2024
59275b8
Add chess requirement to test
abisca Feb 15, 2024
faf0c51
Update lib/Dialect/AIE/Transforms/AIELowerCascadeFlows.cpp
AndraBisca Feb 15, 2024
5d31e23
Test fix
abisca Feb 15, 2024
f03ae64
Update .td descriptions of ops
AndraBisca Feb 19, 2024
36f9456
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cascad…
AndraBisca Feb 19, 2024
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11 changes: 11 additions & 0 deletions include/aie/Dialect/AIE/IR/AIEAttrs.td
Original file line number Diff line number Diff line change
Expand Up @@ -144,4 +144,15 @@ def BDDimLayoutArrayArrayAttr : ArrayOfAttr<
/*eltName*/BDDimLayoutArrayAttr.cppClassName
>;

def CascadeDir: I32EnumAttr<"CascadeDir", "Directions for cascade",
[
I32EnumAttrCase<"South", 0>,
I32EnumAttrCase<"West", 1>,
I32EnumAttrCase<"North", 2>,
I32EnumAttrCase<"East", 3>
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]> {

let cppNamespace = "xilinx::AIE";
}

#endif // AIE_ATTRS
24 changes: 24 additions & 0 deletions include/aie/Dialect/AIE/IR/AIEOps.td
Original file line number Diff line number Diff line change
Expand Up @@ -1343,6 +1343,30 @@ def AIE_PutStreamOp: AIE_Op<"put_stream", [HasParent<"CoreOp">]> {
}];
}

def AIE_ConfigureCascadeOp: AIE_Op<"configure_cascade", [HasParent<"DeviceOp">]> {
let summary = "An op to configure the input and output directions of the cascade for a single AIE tile";
let description = [{
An operation to configure the cascade on a single tile in both the input and the output
directions.

Example:
```
%tile00 = aie.tile(1, 3)
aie.configure_cascade(%tile00, West, East)
```
Configures the input cascade port of %tile00 to the West direction, and the output port to the East direction.
}];

let arguments = (
ins Index:$tile,
CascadeDir:$inputDir,
CascadeDir:$outputDir
);
let results = (outs);
let hasVerifier = 1;
let assemblyFormat = [{ `(` $tile `,` $inputDir `,` $outputDir `)` attr-dict }];
}

def AIE_GetCascadeOp: AIE_Op<"get_cascade", [HasParent<"CoreOp">]>, Results<(outs AnyType:$cascadeValue)> {
let summary = "An op to read from a cascading stream from a neighboring core";
let description = [{
Expand Down
24 changes: 24 additions & 0 deletions lib/Dialect/AIE/IR/AIEDialect.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -864,6 +864,30 @@ ObjectFifoCreateOp ObjectFifoRegisterProcessOp::getObjectFifo() {
return {};
}

//===----------------------------------------------------------------------===//
// ConfigureCascadeOp
//===----------------------------------------------------------------------===//

LogicalResult ConfigureCascadeOp::verify() {
const auto &targetModel = getTargetModel(*this);
CascadeDir inputDir = getInputDir();
CascadeDir outputDir = getOutputDir();
if (targetModel.getTargetArch() == AIEArch::AIE2) {
if (inputDir == CascadeDir::South || inputDir == CascadeDir::East) {
return emitOpError("input direction of cascade must be North or West on ")
<< stringifyAIEArch(targetModel.getTargetArch());
}
if (outputDir == CascadeDir::North || outputDir == CascadeDir::West) {
return emitOpError("output direction of cascade must be South or East on ")
<< stringifyAIEArch(targetModel.getTargetArch());
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}
} else {
return emitOpError("cascade not supported in ")
<< stringifyAIEArch(targetModel.getTargetArch());
}
return success();
}

//===----------------------------------------------------------------------===//
// PutCascadeOp
//===----------------------------------------------------------------------===//
Expand Down
16 changes: 16 additions & 0 deletions lib/Targets/AIETargetXAIEV2.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -765,6 +765,22 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
output << "return XAIE_OK;\n";
output << "} // mlir_aie_configure_switchboxes\n\n";

//---------------------------------------------------------------------------
// mlir_aie_configure_cascade
//---------------------------------------------------------------------------
output << "int mlir_aie_configure_cascade(" << ctx_p << ") {\n";
for (auto configOp : targetOp.getOps<ConfigureCascadeOp>()) {
TileOp tile = dyn_cast<TileOp>(configOp.getTile().getDefiningOp());
int col = tile.colIndex();
int row = tile.rowIndex();
output << "XAie_CoreConfigAccumulatorControl(" << deviceInstRef << ", "
<< "XAie_TileLoc(" << col << ", " << row << "), "
<< stringifyCascadeDir(configOp.getInputDir()).upper() << ", "
<< stringifyCascadeDir(configOp.getOutputDir()).upper() << ");\n";
}
output << "return XAIE_OK;\n";
output << "} // mlir_aie_configure_cascade\n\n";

//---------------------------------------------------------------------------
// Output Buffer Accessors
//---------------------------------------------------------------------------
Expand Down
35 changes: 35 additions & 0 deletions test/dialect/AIE/bad_cascade.mlir
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
//===- bad_cascade.mlir ----------------------------------------*- MLIR -*-===//
//
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2024 Advanced Micro Devices, Inc.
//
//===----------------------------------------------------------------------===//

// RUN: not aie-opt -split-input-file %s 2>&1 | FileCheck %s
// CHECK: error{{.*}}'aie.configure_cascade' op input direction of cascade must be North or West on AIE2

aie.device(xcve2802) {
%t13 = aie.tile(1, 3)
aie.configure_cascade(%t13, East, South)
}

// -----

// CHECK: error{{.*}}'aie.configure_cascade' op output direction of cascade must be South or East on AIE2

aie.device(xcve2802) {
%t13 = aie.tile(1, 3)
aie.configure_cascade(%t13, North, West)
}

// -----

// CHECK: error{{.*}}'aie.configure_cascade' op cascade not supported in AIE1

aie.device(xcvc1902) {
%t13 = aie.tile(1, 3)
aie.configure_cascade(%t13, North, East)
}
20 changes: 20 additions & 0 deletions test/dialect/AIE/cascade_configure.mlir
Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@
//===- cascade_configure.mlir -----------------------------------*- MLIR -*-===//
//
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2024 Advanced Micro Devices, Inc.
//
//===----------------------------------------------------------------------===//

// RUN: aie-opt %s

module @test {
aie.device(xcve2802) {
%t13 = aie.tile(1, 3)
%t23 = aie.tile(2, 3)
aie.configure_cascade(%t13, West, East)
aie.configure_cascade(%t23, North, South)
}
}
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