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Zero padding on MemTiles #1874
Zero padding on MemTiles #1874
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Coverage ReportCreated: 2024-11-18 17:50Click here for information about interpreting this report.
Generated by llvm-cov -- llvm version 14.0.0 |
To DO: Cleanup and moving checks to verifier in |
My latest PR that was merged into main has some updates to the documentation and objectfifo python API. Could you please add some similar style documentation for the mem tile padding in the programming guide as well? I think somewhere at the end of Section 2c should be good. This can be a different PR btw, after this one is merged. |
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Looks good! Just these comments to address and it should be good to merge.
@@ -1317,7 +1329,6 @@ struct AIEObjectFifoStatefulTransformPass | |||
auto consumerWireType = WireBundle::DMA; | |||
std::set<TileOp> | |||
objectFifoTiles; // track cores to check for loops during unrolling | |||
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Typo?
@@ -133,7 +133,7 @@ module @ndDMAObjFifoAIE2 { | |||
// this case between two adjacent tiles, we need to use DMAs if a data | |||
// layout transformation with dimensionsToStream and dimensionsFromStream was specified. | |||
aie.objectfifo @of0 (%tile12 dimensionsToStream [<size = 16, stride = 1>, <size = 16, stride = 16>, <size = 1, stride = 1>], // transpose | |||
{%tile13 dimensionsFromStream [<size = 1, stride = 1>]}, | |||
{%tile13 dimensionsFromStream [<size = 1, stride = 1>]}, |
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typo?
This PR introduces the ability to apply zero padding on MemTiles in 3 dimensions. Specifically, it allows padding to be specified at the object FIFO level for MemTile objects through the addition of a
padDimensions
attribute.In python code:
Lowers to:
Padding can also be applied in the runtime sequence using writebds or through dma_bd_chain.