[aievec] to-llvm/to-cpp flow for emulated fp32xfp32 mul elem #1239
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jsetoain
approved these changes
Apr 16, 2024
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| Arguments<(ins VectorOfLengthAndType<[16], [I64]>:$a, | ||
| I32:$shft, | ||
| I32:$sign)>; | ||
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| def I256V32Acc32SrsIntrOp : | ||
| AIEVec2_IntrOp<"I256.v32.acc32.srs", | ||
| [TypeIs<"res", VectorOfLengthAndType<[32], [I8]>>]>, | ||
| Arguments<(ins VectorOfLengthAndType<[16], [I64]>:$lhs, | ||
| Arguments<(ins VectorOfLengthAndType<[16], [I64]>:$a, | ||
| I32:$shft, | ||
| I32:$sign)>; | ||
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| def I512V16Acc64SrsIntrOp : | ||
| AIEVec2_IntrOp<"I512.v16.acc64.srs", | ||
| [TypeIs<"res", VectorOfLengthAndType<[16], [I32]>>]>, | ||
| Arguments<(ins VectorOfLengthAndType<[16], [I64]>:$lhs, | ||
| Arguments<(ins VectorOfLengthAndType<[16], [I64]>:$a, | ||
| I32:$shft, | ||
| I32:$sign)>; | ||
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| def Vector16AccFloatToV16BF16IntrOp : | ||
| AIEVec2_IntrOp<"v16accfloat.to.v16bf16", | ||
| [TypeIs<"res", VectorOfLengthAndType<[16], [BF16]>>]>, | ||
| Arguments<(ins VectorOfLengthAndType<[8], [I64]>:$lhs)>; | ||
| Arguments<(ins VectorOfLengthAndType<[8], [I64]>:$a)>; |
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Nit.: Can we find names for the arguments better than "a"? I also don't understand why the "shift" parameter can't just be named just "shift" instead of "shft".
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I tried to follow the naming convention from the the definition of CPP intrinsics. Here are some examples.
INTRINSIC(v16accfloat) msc_elem_16_2(v32bfloat16 a, v32bfloat16 b, v16accfloat acc1) {
INTRINSIC(v16accfloat) mac_elem_16_2(v32bfloat16 a, v32bfloat16 b, v16accfloat acc1) {
INTRINSIC(v32bfloat16) insert(v32bfloat16 a, int idx, v16bfloat16 b) {
INTRINSIC(v16accfloat) ups_to_v16accfloat(v16bfloat16 a) {
INTRINSIC(v32int16) lsrs(v32acc32 acc, int shft, int sign) {
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But these are not C++ intrinsics, these are LLVM IR intrinsics, and we should do better than "a/b/c" anyway.
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| class AIE2bf16MACConf : | ||
| Arguments<(ins VectorOfLengthAndType<[32], [BF16]>:$lhs, | ||
| VectorOfLengthAndType<[32], [BF16]>:$rhs, | ||
| VectorOfLengthAndType<[8], [I64]>:$acc, | ||
| I32:$conf)>; | ||
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test/unit_tests/aievec_tests/floatxfloat_mul_elem/floatxfloat_mul_elem-peano.mlir
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test/unit_tests/aievec_tests/floatxfloat_mul_elem/floatxfloat_mul_elem.mlir
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This PR add the support to the emulated fp32xfp32 elementwise multiplication going through the to-llvm and to-cpp flow.
Changes: