Skip to content

Commit

Permalink
cervino -> versal_prod
Browse files Browse the repository at this point in the history
  • Loading branch information
@makslevental
makslevental committed Dec 20, 2023
1 parent 0e16882 commit d27c3dd
Show file tree
Hide file tree
Showing 17 changed files with 28 additions and 28 deletions.
2 changes: 1 addition & 1 deletion reference_designs/MM_2x2/circuit_switched_version/aie.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//

// REQUIRES: valid_xchess_license
// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc
// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc
// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

Expand Down
2 changes: 1 addition & 1 deletion reference_designs/MM_2x2/objectFifo_circuit_switched_version/aie.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//

// REQUIRES: valid_xchess_license
// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc
// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc
// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

Expand Down
2 changes: 1 addition & 1 deletion reference_designs/MM_2x2/packet_switched_version/aie.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
//===----------------------------------------------------------------------===//

// REQUIRES: valid_xchess_license
// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc
// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc
// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

Expand Down
6 changes: 3 additions & 3 deletions reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,14 +14,14 @@ f32: f32_chess f32.elf
build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap.cc ./hdiff_flux.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux_fp32.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux_fp32.cc

i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \
Expand Down
2 changes: 1 addition & 1 deletion reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/sim.tcl
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
iss::create %PROCESSORNAME% iss
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss fileinput add SCD 0 -field -file ./dataset_256x256x64.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0
iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer
#iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0
Expand Down
6 changes: 3 additions & 3 deletions reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,14 +15,14 @@ f32: f32_chess f32.elf
build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff_fp32.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff_fp32.cc


i32.elf:
Expand Down
2 changes: 1 addition & 1 deletion reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/sim.tcl
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
iss::create %PROCESSORNAME% iss
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss fileinput add SCD 0 -field -file ./dataset_1x256x6.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0
iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer
#iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0
Expand Down
6 changes: 3 additions & 3 deletions reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,14 +14,14 @@ f32: f32_chess f32.elf
build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff_fp32.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff_fp32.cc


i32.elf:
Expand Down
2 changes: 1 addition & 1 deletion reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/sim.tcl
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
iss::create %PROCESSORNAME% iss
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss fileinput add SCD 0 -field -file ./dataset_256x256x64.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0
iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer
#iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0
Expand Down
4 changes: 2 additions & 2 deletions reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong_scaled/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,11 @@ all: test.elf
build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl


chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc

test.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \
Expand Down
6 changes: 3 additions & 3 deletions reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,14 +14,14 @@ f32: f32_chess f32.elf
build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc

i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \
Expand Down
2 changes: 1 addition & 1 deletion reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/sim.tcl
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
iss::create %PROCESSORNAME% iss
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss fileinput add SCD 0 -field -file ./dataset_256x256x64.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0
iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer
#iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0
Expand Down
6 changes: 3 additions & 3 deletions reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong_scaled/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,14 +14,14 @@ f32: f32_chess f32.elf
build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc

i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_$(b).mlir \
Expand Down
2 changes: 1 addition & 1 deletion reference_designs/idct/aie.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
//===----------------------------------------------------------------------===//

// REQUIRES: valid_xchess_license && jackl
// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/kernel.cc %S/dequant.cc %S/pass.cc
// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/kernel.cc %S/dequant.cc %S/pass.cc
// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

Expand Down
2 changes: 1 addition & 1 deletion reference_designs/idct/objectFifo_circuit_switched_version/aie.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
//===----------------------------------------------------------------------===//

// REQUIRES: valid_xchess_license && jackl
// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc %S/../dequant.cc %S/../pass.cc
// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc %S/../dequant.cc %S/../pass.cc
// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

Expand Down
2 changes: 1 addition & 1 deletion tutorials/tutorial-9/external_kernel/sim.tcl
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

iss::create %PROCESSORNAME% iss
#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath %XILINX_VITIS%/aietools/data/aie_ml/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss step -1
iss profile save test.prf
Expand Down
2 changes: 1 addition & 1 deletion tutorials/tutorial-9/matmul_kernel/sim.tcl
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

iss::create %PROCESSORNAME% iss
#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath %XILINX_VITIS%/aietools/data/aie_ml/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss step -1
iss profile save test.prf
Expand Down

0 comments on commit d27c3dd

Please sign in to comment.