Cleanup TOSA regressions (#726)

* Move tests to the correct location
* Replace the lowering pipeline to the lit.local.cfg defined one
* Remove the XFAIL marks for the XPASS tests
* Fix tosa.mul shift=0 from i32 to i8

test/Integration/Dialect/TOSA/bf16_abs_v16/bf16_abs.mlir

@@ -0,0 +1,14 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 85
+
+func.func @dut(%arg0: tensor<1024xbf16>) -> (tensor<1024xbf16>) {
+  %0 = "tosa.abs" (%arg0) : (tensor<1024xbf16>) -> tensor<1024xbf16>
+  return %0 : tensor<1024xbf16>
+}
+

test/Integration/Dialect/TOSA/bf16_abs_v32/bf16_abs.mlir

@@ -0,0 +1,14 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v32% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 89
+
+func.func @dut(%arg0: tensor<1024xbf16>) -> (tensor<1024xbf16>) {
+  %0 = "tosa.abs" (%arg0) : (tensor<1024xbf16>) -> tensor<1024xbf16>
+  return %0 : tensor<1024xbf16>
+}
+

test/Integration/Dialect/TOSA/bf16_erf_v16/bf16_erf.mlir

@@ -0,0 +1,15 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out"
+// RUN: clang++ %S/dut_ref.cc -o dut_ref
+// RUN: ./dut_ref >& check.stdout
+// RUN: FileCheck --input-file=./check.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 1134
+
+func.func @dut(%arg0: tensor<1024xbf16>) -> (tensor<1024xbf16>) {
+  %0 = tosa.erf %arg0 : (tensor<1024xbf16>) -> tensor<1024xbf16>
+  return %0 : tensor<1024xbf16>
+}

test/Integration/Dialect/TOSA/bf16_erf_v32/bf16_erf.mlir

@@ -0,0 +1,15 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v32% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out"
+// RUN: clang++ %S/dut_ref.cc -o dut_ref
+// RUN: ./dut_ref >& check.stdout
+// RUN: FileCheck --input-file=./check.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 1253
+
+func.func @dut(%arg0: tensor<1024xbf16>) -> (tensor<1024xbf16>) {
+  %0 = tosa.erf %arg0 : (tensor<1024xbf16>) -> tensor<1024xbf16>
+  return %0 : tensor<1024xbf16>
+}

test/Integration/Dialect/TOSA/bf16_tanh/bf16_tanh.mlir

@@ -0,0 +1,13 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 %aie_runtime_lib%/AIE2/lut_based_ops.cpp -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 807
+
+func.func @dut(%arg0: tensor<1024xbf16>) -> (tensor<1024xbf16>) {
+  %0 = "tosa.tanh"(%arg0) : (tensor<1024xbf16>) -> tensor<1024xbf16>
+  return %0 : tensor<1024xbf16>
+}

test/Integration/Dialect/TOSA/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir

@@ -3,7 +3,8 @@
 
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
-// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir
+// RUN: aie-opt %s %tosa-to-linalg% -o %t/linalg.mlir >& aie-opt.stdout
+// RUN: aie-opt %t/linalg.mlir %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir
 // RUN: aie-translate %t/aievec.mlir -aieml=true --aievec-to-cpp -o %t/dut.cc
 // RUN: cd %t; xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
@@ -12,7 +13,7 @@
 
 module {
   func.func @dut(%arg0: tensor<1024xbf16>, %arg1: tensor<1024xbf16>) -> (tensor<1024xbf16>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<1024xbf16>, tensor<1024xbf16>)  -> (tensor<1024xbf16>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<1024xbf16>, tensor<1024xbf16>)  -> (tensor<1024xbf16>)
     return %1 : tensor<1024xbf16>
   }
 }

test/Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1/bf16xbf16_mul_elem_2d_broadcast_1d_unit_dim.mlir

@@ -14,7 +14,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xbf16>, %arg1: tensor<1xbf16>) -> (tensor<16x1024xbf16>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1>} : (tensor<1xbf16>)  -> (tensor<1x1xbf16>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xbf16>, tensor<1x1xbf16>)  -> (tensor<16x1024xbf16>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xbf16>, tensor<1x1xbf16>)  -> (tensor<16x1024xbf16>)
     return %1 : tensor<16x1024xbf16>
   }
 }

test/Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1/bf16xbf16_mul_elem_2d_broadcast_scalar.mlir

@@ -14,7 +14,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xbf16>, %arg1: tensor<bf16>) -> (tensor<16x1024xbf16>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1>} : (tensor<bf16>)  -> (tensor<1x1xbf16>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xbf16>, tensor<1x1xbf16>)  -> (tensor<16x1024xbf16>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xbf16>, tensor<1x1xbf16>)  -> (tensor<16x1024xbf16>)
     return %1 : tensor<16x1024xbf16>
   }
 }

test/Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1024/bf16xbf16_mul_elem_2d_broadcast_1d.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir
@@ -14,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<16x1024xbf16>, %arg1: tensor<1024xbf16>) -> (tensor<16x1024xbf16>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<16x1024xbf16>, tensor<1024xbf16>)  -> (tensor<16x1024xbf16>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<16x1024xbf16>, tensor<1024xbf16>)  -> (tensor<16x1024xbf16>)
     return %1 : tensor<16x1024xbf16>
   }
 }

test/Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1024/bf16xbf16_mul_elem_2d_broadcast_1d_reshape.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xbf16>, %arg1: tensor<1024xbf16>) -> (tensor<16x1024xbf16>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1024>} : (tensor<1024xbf16>)  -> (tensor<1x1024xbf16>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xbf16>, tensor<1x1024xbf16>)  -> (tensor<16x1024xbf16>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xbf16>, tensor<1x1024xbf16>)  -> (tensor<16x1024xbf16>)
     return %1 : tensor<16x1024xbf16>
   }
 }

test/Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1024/bf16xbf16_mul_elem_2d_broadcast_2d.mlir

@@ -12,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<16x1024xbf16>, %arg1: tensor<1x1024xbf16>) -> (tensor<16x1024xbf16>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<16x1024xbf16>, tensor<1x1024xbf16>)  -> (tensor<16x1024xbf16>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<16x1024xbf16>, tensor<1x1024xbf16>)  -> (tensor<16x1024xbf16>)
     return %1 : tensor<16x1024xbf16>
   }
 }

test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_16x1024_broadcast_1024/bf16xbf16_sub_elem_2d_broadcast_1d.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir

test/Integration/Dialect/TOSA/float_abs_v16/float_abs.mlir

@@ -0,0 +1,14 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 150
+
+func.func @dut(%arg0: tensor<1024xf32>) -> (tensor<1024xf32>) {
+  %0 = "tosa.abs" (%arg0) : (tensor<1024xf32>) -> tensor<1024xf32>
+  return %0 : tensor<1024xf32>
+}
+

test/Integration/Dialect/TOSA/floatxfloat_sub_elem_16x1024_broadcast_1024/floatxfloat_sub_elem_2d_broadcast_1d.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir

test/Integration/Dialect/TOSA/i16_abs_v32/i16_abs.mlir

@@ -0,0 +1,14 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v32% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 150
+
+func.func @dut(%arg0: tensor<1024xi16>) -> (tensor<1024xi16>) {
+  %0 = "tosa.abs" (%arg0) : (tensor<1024xi16>) -> tensor<1024xi16>
+  return %0 : tensor<1024xi16>
+}
+

test/Integration/Dialect/TOSA/i16xi16_mul_elem/i16xi16_mul_elem.mlir

@@ -12,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<1024xi16>, %arg1: tensor<1024xi16>) -> (tensor<1024xi16>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<1024xi16>, tensor<1024xi16>)  -> (tensor<1024xi16>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<1024xi16>, tensor<1024xi16>)  -> (tensor<1024xi16>)
     return %1 : tensor<1024xi16>
   }
 }

test/Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1/i16xi16_mul_elem_2d_broadcast_1d_unit_dim.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xi16>, %arg1: tensor<1xi16>) -> (tensor<16x1024xi16>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1>} : (tensor<1xi16>)  -> (tensor<1x1xi16>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xi16>, tensor<1x1xi16>)  -> (tensor<16x1024xi16>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xi16>, tensor<1x1xi16>)  -> (tensor<16x1024xi16>)
     return %1 : tensor<16x1024xi16>
   }
 }

test/Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1/i16xi16_mul_elem_2d_broadcast_scalar.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xi16>, %arg1: tensor<i16>) -> (tensor<16x1024xi16>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1>} : (tensor<i16>)  -> (tensor<1x1xi16>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xi16>, tensor<1x1xi16>)  -> (tensor<16x1024xi16>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xi16>, tensor<1x1xi16>)  -> (tensor<16x1024xi16>)
     return %1 : tensor<16x1024xi16>
   }
 }

test/Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1024/i16xi16_mul_elem_2d_broadcast_1d.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v32% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir
@@ -14,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<16x1024xi16>, %arg1: tensor<1024xi16>) -> (tensor<16x1024xi16>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<16x1024xi16>, tensor<1024xi16>)  -> (tensor<16x1024xi16>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<16x1024xi16>, tensor<1024xi16>)  -> (tensor<16x1024xi16>)
     return %1 : tensor<16x1024xi16>
   }
 }

test/Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1024/i16xi16_mul_elem_2d_broadcast_1d_reshape.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xi16>, %arg1: tensor<1024xi16>) -> (tensor<16x1024xi16>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1024>} : (tensor<1024xi16>)  -> (tensor<1x1024xi16>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xi16>, tensor<1x1024xi16>)  -> (tensor<16x1024xi16>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xi16>, tensor<1x1024xi16>)  -> (tensor<16x1024xi16>)
     return %1 : tensor<16x1024xi16>
   }
 }

test/Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1024/i16xi16_mul_elem_2d_broadcast_2d.mlir

@@ -12,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<16x1024xi16>, %arg1: tensor<1x1024xi16>) -> (tensor<16x1024xi16>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<16x1024xi16>, tensor<1x1024xi16>)  -> (tensor<16x1024xi16>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<16x1024xi16>, tensor<1x1024xi16>)  -> (tensor<16x1024xi16>)
     return %1 : tensor<16x1024xi16>
   }
 }

test/Integration/Dialect/TOSA/i16xi16_mul_elem_i32/i16xi16_mul_elem_i32.mlir

@@ -12,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<1024xi16>, %arg1: tensor<1024xi16>) -> (tensor<1024xi32>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<1024xi16>, tensor<1024xi16>)  -> (tensor<1024xi32>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<1024xi16>, tensor<1024xi16>)  -> (tensor<1024xi32>)
     return %1 : tensor<1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i16xi16_sub_elem_16x1024_broadcast_1024/i16xi16_sub_elem_2d_broadcast_1d.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v32% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir

test/Integration/Dialect/TOSA/i16xi32_mul_elem/i16xi32_mul_elem.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<1024xi16>, %arg1: tensor<1024xi32>) -> (tensor<1024xi32>) {
     %0 = "tosa.cast"(%arg0) : (tensor<1024xi16>) -> tensor<1024xi32>
-    %2 = "tosa.mul"(%0,%arg1) {shift = 0 : i32} : (tensor<1024xi32>, tensor<1024xi32>)  -> (tensor<1024xi32>)
+    %2 = "tosa.mul"(%0,%arg1) {shift = 0 : i8} : (tensor<1024xi32>, tensor<1024xi32>)  -> (tensor<1024xi32>)
     return %2 : tensor<1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i16xi32_mul_elem/i32xi16_mul_elem.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<1024xi16>, %arg1: tensor<1024xi32>) -> (tensor<1024xi32>) {
     %0 = "tosa.cast"(%arg0) : (tensor<1024xi16>) -> tensor<1024xi32>
-    %2 = "tosa.mul"(%arg1, %0) {shift = 0 : i32} : (tensor<1024xi32>, tensor<1024xi32>)  -> (tensor<1024xi32>)
+    %2 = "tosa.mul"(%arg1, %0) {shift = 0 : i8} : (tensor<1024xi32>, tensor<1024xi32>)  -> (tensor<1024xi32>)
     return %2 : tensor<1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i32_abs_v16/i32_abs.mlir

@@ -0,0 +1,14 @@
+// REQUIRES: valid_xchess_license
+// RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc
+// RUN: mkdir -p data
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+// Cycle count: 278
+
+func.func @dut(%arg0: tensor<1024xi32>) -> (tensor<1024xi32>) {
+  %0 = "tosa.abs" (%arg0) : (tensor<1024xi32>) -> tensor<1024xi32>
+  return %0 : tensor<1024xi32>
+}
+

test/Integration/Dialect/TOSA/i32xi32_mul_elem/i32xi32_mul_elem.mlir

@@ -12,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<1024xi32>, %arg1: tensor<1024xi32>) -> (tensor<1024xi32>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<1024xi32>, tensor<1024xi32>)  -> (tensor<1024xi32>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<1024xi32>, tensor<1024xi32>)  -> (tensor<1024xi32>)
     return %1 : tensor<1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1/i32xi32_mul_elem_2d_broadcast_1d_unit_dim.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xi32>, %arg1: tensor<1xi32>) -> (tensor<16x1024xi32>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1>} : (tensor<1xi32>)  -> (tensor<1x1xi32>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xi32>, tensor<1x1xi32>)  -> (tensor<16x1024xi32>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xi32>, tensor<1x1xi32>)  -> (tensor<16x1024xi32>)
     return %1 : tensor<16x1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1/i32xi32_mul_elem_2d_broadcast_scalar.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xi32>, %arg1: tensor<i32>) -> (tensor<16x1024xi32>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1>} : (tensor<i32>)  -> (tensor<1x1xi32>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xi32>, tensor<1x1xi32>)  -> (tensor<16x1024xi32>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xi32>, tensor<1x1xi32>)  -> (tensor<16x1024xi32>)
     return %1 : tensor<16x1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1024/i32xi32_mul_elem_2d_broadcast_1d.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir
@@ -14,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<16x1024xi32>, %arg1: tensor<1024xi32>) -> (tensor<16x1024xi32>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<16x1024xi32>, tensor<1024xi32>)  -> (tensor<16x1024xi32>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<16x1024xi32>, tensor<1024xi32>)  -> (tensor<16x1024xi32>)
     return %1 : tensor<16x1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1024/i32xi32_mul_elem_2d_broadcast_1d_reshape.mlir

@@ -13,7 +13,7 @@
 module {
   func.func @dut(%arg0: tensor<16x1024xi32>, %arg1: tensor<1024xi32>) -> (tensor<16x1024xi32>) {
     %0 = "tosa.reshape"(%arg1) { new_shape = array<i64: 1, 1024>} : (tensor<1024xi32>)  -> (tensor<1x1024xi32>)
-    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i32} : (tensor<16x1024xi32>, tensor<1x1024xi32>)  -> (tensor<16x1024xi32>)
+    %1 = "tosa.mul"(%arg0,%0) {shift = 0 : i8} : (tensor<16x1024xi32>, tensor<1x1024xi32>)  -> (tensor<16x1024xi32>)
     return %1 : tensor<16x1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1024/i32xi32_mul_elem_2d_broadcast_2d.mlir

@@ -12,7 +12,7 @@
 
 module {
   func.func @dut(%arg0: tensor<16x1024xi32>, %arg1: tensor<1x1024xi32>) -> (tensor<16x1024xi32>) {
-    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i32} : (tensor<16x1024xi32>, tensor<1x1024xi32>)  -> (tensor<16x1024xi32>)
+    %1 = "tosa.mul"(%arg0,%arg1) {shift = 0 : i8} : (tensor<16x1024xi32>, tensor<1x1024xi32>)  -> (tensor<16x1024xi32>)
     return %1 : tensor<16x1024xi32>
   }
 }

test/Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_1d_v16.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v16% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir

test/Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_1d_v32.mlir

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 // Copyright (C) 2023, Advanced Micro Devices, Inc.
 
-// Need the later LLVM version from `catch up to TOM MLIR #590`
-// XFAIL: *
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data
 // RUN: aie-opt %s %tosa-to-linalg% | aie-opt %linalg-to-vector-v32% --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o %t/aievec.mlir