Fix some test failures (#614)

Xilinx · Aug 31, 2023 · 8329ef2 · 8329ef2
1 parent 732f8be
commit 8329ef2
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Showing 7 changed files with 13 additions and 11 deletions.
diff --git a/test/unit_tests/aie/21_shim_dma_packet/test.cpp b/test/unit_tests/aie/21_shim_dma_packet/test.cpp
@@ -5,7 +5,9 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "memory_allocator.h"
 #include "test_library.h"
+
 #include <cassert>
 #include <cmath>
 #include <cstdio>
@@ -18,7 +20,6 @@
 #include <xaiengine.h>
 
 #include "aie_inc.cpp"
-#include "memory_allocator.h"
 
 int main(int argc, char *argv[]) {
   unsigned iter_num = 1;

diff --git a/test/unit_tests/aie/24_host_loop/aie.mlir b/test/unit_tests/aie/24_host_loop/aie.mlir
@@ -11,7 +11,7 @@
 // RUN: aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
-module @host_loop {
+AIE.device(xcvc1902) {
     %tile34 = AIE.tile(3, 4)
     %tile70 = AIE.tile(7, 0)
 
@@ -28,8 +28,8 @@ module @host_loop {
     %ext_buf70_in  = AIE.external_buffer {sym_name = "ddr_test_buffer_in"}: memref<256xi32>
     %ext_buf70_out = AIE.external_buffer {sym_name = "ddr_test_buffer_out"}: memref<256xi32>
 
-    AIE.objectFifo @of_in (%tile70, {%tile34}, 1) : !AIE.objectFifo<memref<256xi32>>
-    AIE.objectFifo @of_out (%tile34, {%tile70}, 1) : !AIE.objectFifo<memref<256xi32>>
+    AIE.objectFifo @of_in (%tile70, {%tile34}, 1 : i32) : !AIE.objectFifo<memref<256xi32>>
+    AIE.objectFifo @of_out (%tile34, {%tile70}, 1 : i32) : !AIE.objectFifo<memref<256xi32>>
 
     AIE.objectFifo.registerExternalBuffers @of_in (%tile70, {%ext_buf70_in}) : (memref<256xi32>)
     AIE.objectFifo.registerExternalBuffers @of_out (%tile70, {%ext_buf70_out}) : (memref<256xi32>)

diff --git a/test/unit_tests/aie/25_host_multirate/aie.mlir b/test/unit_tests/aie/25_host_multirate/aie.mlir
@@ -11,7 +11,7 @@
 // RUN: aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
-module @host_multirate {
+AIE.device(xcvc1902) {
     %tile34 = AIE.tile(3, 4)
     %tile70 = AIE.tile(7, 0)
 
@@ -30,8 +30,8 @@ module @host_multirate {
     %ext_buf70_in  = AIE.external_buffer {sym_name = "ddr_test_buffer_in"}: memref<256xi32>
     %ext_buf70_out = AIE.external_buffer {sym_name = "ddr_test_buffer_out"}: memref<64xi32>
 
-    AIE.objectFifo @of_in (%tile70, {%tile34}, 1) : !AIE.objectFifo<memref<64xi32>>
-    AIE.objectFifo @of_out (%tile34, {%tile70}, 1) : !AIE.objectFifo<memref<64xi32>>
+    AIE.objectFifo @of_in (%tile70, {%tile34}, 1 : i32) : !AIE.objectFifo<memref<64xi32>>
+    AIE.objectFifo @of_out (%tile34, {%tile70}, 1 : i32) : !AIE.objectFifo<memref<64xi32>>
 
     AIE.objectFifo.registerExternalBuffers @of_in (%tile70, {%ext_buf70_in}) : (memref<256xi32>)
     AIE.objectFifo.registerExternalBuffers @of_out (%tile70, {%ext_buf70_out}) : (memref<64xi32>)

diff --git a/test/unit_tests/aie/27_single_L1_single_lock/aieWithWorkaround.mlir b/test/unit_tests/aie/27_single_L1_single_lock/aieWithWorkaround.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: aiecc.py --sysroot=%VITIS_SYSROOT% --host-target=aarch64-linux-gnu %s -I%host_runtime_lib% %extraAieCcFlags% %host_runtime_lib%/test_library.cpp %S/test.cpp -o test.elf
+// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
 module @test27_simple_shim_dma_single_lock {

diff --git a/test/unit_tests/aie/28_multidepth_objectFifos/multi_depth/aie.mlir b/test/unit_tests/aie/28_multidepth_objectFifos/multi_depth/aie.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
+// RUN: aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
 module @multi_depth {

diff --git a/test/unit_tests/aie/28_multidepth_objectFifos/single_depth/aie.mlir b/test/unit_tests/aie/28_multidepth_objectFifos/single_depth/aie.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
+// RUN: aiecc.py -j4 %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
 module @single_depth {

diff --git a/test/unit_tests/aie2/07_shim_dma_core_function_with_loop/test.cpp b/test/unit_tests/aie2/07_shim_dma_core_function_with_loop/test.cpp
@@ -8,7 +8,9 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "memory_allocator.h"
 #include "test_library.h"
+
 #include <cassert>
 #include <cmath>
 #include <cstdio>
@@ -21,7 +23,6 @@
 #include <xaiengine.h>
 
 #include "aie_inc.cpp"
-#include "memory_allocator.h"
 
 int main(int argc, char *argv[]) {
   printf("test start.\n");